1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c43f6c8STom Warren /* 36c43f6c8STom Warren * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved. 46c43f6c8STom Warren */ 56c43f6c8STom Warren 66c43f6c8STom Warren #ifndef _TEGRA210_MC_H_ 76c43f6c8STom Warren #define _TEGRA210_MC_H_ 86c43f6c8STom Warren 96c43f6c8STom Warren /** 106c43f6c8STom Warren * Defines the memory controller registers we need/care about 116c43f6c8STom Warren */ 126c43f6c8STom Warren struct mc_ctlr { 136c43f6c8STom Warren u32 reserved0[4]; /* offset 0x00 - 0x0C */ 146c43f6c8STom Warren u32 mc_smmu_config; /* offset 0x10 */ 156c43f6c8STom Warren u32 mc_smmu_tlb_config; /* offset 0x14 */ 166c43f6c8STom Warren u32 mc_smmu_ptc_config; /* offset 0x18 */ 176c43f6c8STom Warren u32 mc_smmu_ptb_asid; /* offset 0x1C */ 186c43f6c8STom Warren u32 mc_smmu_ptb_data; /* offset 0x20 */ 196c43f6c8STom Warren u32 reserved1[3]; /* offset 0x24 - 0x2C */ 206c43f6c8STom Warren u32 mc_smmu_tlb_flush; /* offset 0x30 */ 216c43f6c8STom Warren u32 mc_smmu_ptc_flush; /* offset 0x34 */ 226c43f6c8STom Warren u32 reserved2[6]; /* offset 0x38 - 0x4C */ 236c43f6c8STom Warren u32 mc_emem_cfg; /* offset 0x50 */ 246c43f6c8STom Warren u32 mc_emem_adr_cfg; /* offset 0x54 */ 256c43f6c8STom Warren u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 266c43f6c8STom Warren u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 276c43f6c8STom Warren u32 reserved3[4]; /* offset 0x60 - 0x6C */ 286c43f6c8STom Warren u32 mc_security_cfg0; /* offset 0x70 */ 296c43f6c8STom Warren u32 mc_security_cfg1; /* offset 0x74 */ 306c43f6c8STom Warren u32 reserved4[6]; /* offset 0x7C - 0x8C */ 316c43f6c8STom Warren u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 326c43f6c8STom Warren u32 reserved5[74]; /* offset 0x100 - 0x224 */ 336c43f6c8STom Warren u32 mc_smmu_translation_enable_0; /* offset 0x228 */ 346c43f6c8STom Warren u32 mc_smmu_translation_enable_1; /* offset 0x22C */ 356c43f6c8STom Warren u32 mc_smmu_translation_enable_2; /* offset 0x230 */ 366c43f6c8STom Warren u32 mc_smmu_translation_enable_3; /* offset 0x234 */ 376c43f6c8STom Warren u32 mc_smmu_afi_asid; /* offset 0x238 */ 386c43f6c8STom Warren u32 mc_smmu_avpc_asid; /* offset 0x23C */ 396c43f6c8STom Warren u32 mc_smmu_dc_asid; /* offset 0x240 */ 406c43f6c8STom Warren u32 mc_smmu_dcb_asid; /* offset 0x244 */ 416c43f6c8STom Warren u32 reserved6[2]; /* offset 0x248 - 0x24C */ 426c43f6c8STom Warren u32 mc_smmu_hc_asid; /* offset 0x250 */ 436c43f6c8STom Warren u32 mc_smmu_hda_asid; /* offset 0x254 */ 446c43f6c8STom Warren u32 mc_smmu_isp2_asid; /* offset 0x258 */ 456c43f6c8STom Warren u32 reserved7[2]; /* offset 0x25C - 0x260 */ 466c43f6c8STom Warren u32 mc_smmu_msenc_asid; /* offset 0x264 */ 476c43f6c8STom Warren u32 mc_smmu_nv_asid; /* offset 0x268 */ 486c43f6c8STom Warren u32 mc_smmu_nv2_asid; /* offset 0x26C */ 496c43f6c8STom Warren u32 mc_smmu_ppcs_asid; /* offset 0x270 */ 506c43f6c8STom Warren u32 mc_smmu_sata_asid; /* offset 0x274 */ 516c43f6c8STom Warren u32 reserved8[1]; /* offset 0x278 */ 526c43f6c8STom Warren u32 mc_smmu_vde_asid; /* offset 0x27C */ 536c43f6c8STom Warren u32 mc_smmu_vi_asid; /* offset 0x280 */ 546c43f6c8STom Warren u32 mc_smmu_vic_asid; /* offset 0x284 */ 556c43f6c8STom Warren u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ 566c43f6c8STom Warren u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ 576c43f6c8STom Warren u32 reserved9[1]; /* offset 0x290 */ 586c43f6c8STom Warren u32 mc_smmu_tsec_asid; /* offset 0x294 */ 596c43f6c8STom Warren u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ 606c43f6c8STom Warren u32 reserved10[235]; /* offset 0x29C - 0x644 */ 616c43f6c8STom Warren u32 mc_video_protect_bom; /* offset 0x648 */ 626c43f6c8STom Warren u32 mc_video_protect_size_mb; /* offset 0x64c */ 636c43f6c8STom Warren u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 646c43f6c8STom Warren }; 656c43f6c8STom Warren 666c43f6c8STom Warren #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) 676c43f6c8STom Warren 686c43f6c8STom Warren #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) 696c43f6c8STom Warren #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) 706c43f6c8STom Warren 716c43f6c8STom Warren #endif /* _TEGRA210_MC_H_ */ 72