1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c43f6c8STom Warren /* 36c43f6c8STom Warren * (C) Copyright 2013-2015 46c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 56c43f6c8STom Warren */ 66c43f6c8STom Warren 76c43f6c8STom Warren /* Tegra210 high-level function multiplexing */ 86c43f6c8STom Warren 96c43f6c8STom Warren #ifndef _TEGRA210_FUNCMUX_H_ 106c43f6c8STom Warren #define _TEGRA210_FUNCMUX_H_ 116c43f6c8STom Warren 126c43f6c8STom Warren #include <asm/arch-tegra/funcmux.h> 136c43f6c8STom Warren 146c43f6c8STom Warren /* Configs supported by the func mux */ 156c43f6c8STom Warren enum { 166c43f6c8STom Warren FUNCMUX_DEFAULT = 0, /* default config */ 176c43f6c8STom Warren 186c43f6c8STom Warren /* UART configs */ 196c43f6c8STom Warren FUNCMUX_UART1_UART1 = 0, 206c43f6c8STom Warren FUNCMUX_UART4_UART4 = 0, 216c43f6c8STom Warren }; 226c43f6c8STom Warren #endif /* _TEGRA210_FUNCMUX_H_ */ 23