1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010-2015
4  * NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _TEGRA210_FLOW_H_
8 #define _TEGRA210_FLOW_H_
9 
10 struct flow_ctlr {
11 	u32 halt_cpu_events;	/* offset 0x00 */
12 	u32 halt_cop_events;	/* offset 0x04 */
13 	u32 cpu_csr;		/* offset 0x08 */
14 	u32 cop_csr;		/* offset 0x0c */
15 	u32 xrq_events;		/* offset 0x10 */
16 	u32 halt_cpu1_events;	/* offset 0x14 */
17 	u32 cpu1_csr;		/* offset 0x18 */
18 	u32 halt_cpu2_events;	/* offset 0x1c */
19 	u32 cpu2_csr;		/* offset 0x20 */
20 	u32 halt_cpu3_events;	/* offset 0x24 */
21 	u32 cpu3_csr;		/* offset 0x28 */
22 	u32 cluster_control;	/* offset 0x2c */
23 	u32 halt_cop1_events;	/* offset 0x30 */
24 	u32 halt_cop1_csr;	/* offset 0x34 */
25 	u32 cpu_pwr_csr;	/* offset 0x38 */
26 	u32 mpid;		/* offset 0x3c */
27 	u32 ram_repair;		/* offset 0x40 */
28 };
29 
30 /* HALT_COP_EVENTS_0, 0x04 */
31 #define EVENT_MSEC		(1 << 24)
32 #define EVENT_USEC		(1 << 25)
33 #define EVENT_JTAG		(1 << 28)
34 #define EVENT_MODE_STOP		(2 << 29)
35 
36 /* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
37 #define ACTIVE_LP		(1 << 0)
38 
39 /* CPUn_CSR_0 */
40 #define CSR_ENABLE		(1 << 0)
41 #define CSR_IMMEDIATE_WAKE	(1 << 3)
42 #define CSR_WAIT_WFI_SHIFT	8
43 
44 #endif /*  _TEGRA210_FLOW_H_ */
45