1 /*
2  * (C) Copyright 2010-2015
3  * NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7 
8 /* Tegra210 clock control definitions */
9 
10 #ifndef _TEGRA210_CLOCK_H_
11 #define _TEGRA210_CLOCK_H_
12 
13 #include <asm/arch-tegra/clock.h>
14 
15 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
16 #define OSC_FREQ_SHIFT          28
17 #define OSC_FREQ_MASK           (0xF << OSC_FREQ_SHIFT)
18 
19 /* PLL bits that differ from generic clk_rst.h */
20 #define PLLC_RESET		30
21 #define PLLC_IDDQ		27
22 #define PLLD_ENABLE_CLK		21
23 #define PLLD_EN_LCKDET		28
24 
25 int tegra_plle_enable(void);
26 
27 #endif	/* _TEGRA210_CLOCK_H_ */
28