1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 26c43f6c8STom Warren /* 36c43f6c8STom Warren * (C) Copyright 2010-2015 46c43f6c8STom Warren * NVIDIA Corporation <www.nvidia.com> 56c43f6c8STom Warren */ 66c43f6c8STom Warren 76c43f6c8STom Warren /* Tegra210 clock control definitions */ 86c43f6c8STom Warren 96c43f6c8STom Warren #ifndef _TEGRA210_CLOCK_H_ 106c43f6c8STom Warren #define _TEGRA210_CLOCK_H_ 116c43f6c8STom Warren 126c43f6c8STom Warren #include <asm/arch-tegra/clock.h> 136c43f6c8STom Warren 146c43f6c8STom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 156c43f6c8STom Warren #define OSC_FREQ_SHIFT 28 166c43f6c8STom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 176c43f6c8STom Warren 186c43f6c8STom Warren /* PLL bits that differ from generic clk_rst.h */ 196c43f6c8STom Warren #define PLLC_RESET 30 206c43f6c8STom Warren #define PLLC_IDDQ 27 216c43f6c8STom Warren #define PLLD_ENABLE_CLK 21 226c43f6c8STom Warren #define PLLD_EN_LCKDET 28 236c43f6c8STom Warren 246c43f6c8STom Warren int tegra_plle_enable(void); 256c43f6c8STom Warren 266c43f6c8STom Warren #endif /* _TEGRA210_CLOCK_H_ */ 27