1 /* 2 * (C) Copyright 2010, 2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _SDRAM_PARAM_H_ 25 #define _SDRAM_PARAM_H_ 26 27 /* 28 * Defines the number of 32-bit words provided in each set of SDRAM parameters 29 * for arbitration configuration data. 30 */ 31 #define BCT_SDRAM_ARB_CONFIG_WORDS 27 32 33 enum memory_type { 34 MEMORY_TYPE_NONE = 0, 35 MEMORY_TYPE_DDR, 36 MEMORY_TYPE_LPDDR, 37 MEMORY_TYPE_DDR2, 38 MEMORY_TYPE_LPDDR2, 39 MEMORY_TYPE_NUM, 40 MEMORY_TYPE_FORCE32 = 0x7FFFFFFF 41 }; 42 43 /* Defines the SDRAM parameter structure */ 44 struct sdram_params { 45 enum memory_type memory_type; 46 u32 pllm_charge_pump_setup_control; 47 u32 pllm_loop_filter_setup_control; 48 u32 pllm_input_divider; 49 u32 pllm_feedback_divider; 50 u32 pllm_post_divider; 51 u32 pllm_stable_time; 52 u32 emc_clock_divider; 53 u32 emc_auto_cal_interval; 54 u32 emc_auto_cal_config; 55 u32 emc_auto_cal_wait; 56 u32 emc_pin_program_wait; 57 u32 emc_rc; 58 u32 emc_rfc; 59 u32 emc_ras; 60 u32 emc_rp; 61 u32 emc_r2w; 62 u32 emc_w2r; 63 u32 emc_r2p; 64 u32 emc_w2p; 65 u32 emc_rd_rcd; 66 u32 emc_wr_rcd; 67 u32 emc_rrd; 68 u32 emc_rext; 69 u32 emc_wdv; 70 u32 emc_quse; 71 u32 emc_qrst; 72 u32 emc_qsafe; 73 u32 emc_rdv; 74 u32 emc_refresh; 75 u32 emc_burst_refresh_num; 76 u32 emc_pdex2wr; 77 u32 emc_pdex2rd; 78 u32 emc_pchg2pden; 79 u32 emc_act2pden; 80 u32 emc_ar2pden; 81 u32 emc_rw2pden; 82 u32 emc_txsr; 83 u32 emc_tcke; 84 u32 emc_tfaw; 85 u32 emc_trpab; 86 u32 emc_tclkstable; 87 u32 emc_tclkstop; 88 u32 emc_trefbw; 89 u32 emc_quseextra; 90 u32 emc_fbioc_fg1; 91 u32 emc_fbio_dqsib_dly; 92 u32 emc_fbio_dqsib_dly_msb; 93 u32 emc_fbio_quse_dly; 94 u32 emc_fbio_quse_dly_msb; 95 u32 emc_fbio_cfg5; 96 u32 emc_fbio_cfg6; 97 u32 emc_fbio_spare; 98 u32 emc_mrs; 99 u32 emc_emrs; 100 u32 emc_mrw1; 101 u32 emc_mrw2; 102 u32 emc_mrw3; 103 u32 emc_mrw_reset_command; 104 u32 emc_mrw_reset_init_wait; 105 u32 emc_adr_cfg; 106 u32 emc_adr_cfg1; 107 u32 emc_emem_cfg; 108 u32 emc_low_latency_config; 109 u32 emc_cfg; 110 u32 emc_cfg2; 111 u32 emc_dbg; 112 u32 ahb_arbitration_xbar_ctrl; 113 u32 emc_cfg_dig_dll; 114 u32 emc_dll_xform_dqs; 115 u32 emc_dll_xform_quse; 116 u32 warm_boot_wait; 117 u32 emc_ctt_term_ctrl; 118 u32 emc_odt_write; 119 u32 emc_odt_read; 120 u32 emc_zcal_ref_cnt; 121 u32 emc_zcal_wait_cnt; 122 u32 emc_zcal_mrw_cmd; 123 u32 emc_mrs_reset_dll; 124 u32 emc_mrw_zq_init_dev0; 125 u32 emc_mrw_zq_init_dev1; 126 u32 emc_mrw_zq_init_wait; 127 u32 emc_mrs_reset_dll_wait; 128 u32 emc_emrs_emr2; 129 u32 emc_emrs_emr3; 130 u32 emc_emrs_ddr2_dll_enable; 131 u32 emc_mrs_ddr2_dll_reset; 132 u32 emc_emrs_ddr2_ocd_calib; 133 u32 emc_edr2_wait; 134 u32 emc_cfg_clktrim0; 135 u32 emc_cfg_clktrim1; 136 u32 emc_cfg_clktrim2; 137 u32 pmc_ddr_pwr; 138 u32 apb_misc_gp_xm2cfga_padctrl; 139 u32 apb_misc_gp_xm2cfgc_padctrl; 140 u32 apb_misc_gp_xm2cfgc_padctrl2; 141 u32 apb_misc_gp_xm2cfgd_padctrl; 142 u32 apb_misc_gp_xm2cfgd_padctrl2; 143 u32 apb_misc_gp_xm2clkcfg_padctrl; 144 u32 apb_misc_gp_xm2comp_padctrl; 145 u32 apb_misc_gp_xm2vttgen_padctrl; 146 u32 arbitration_config[BCT_SDRAM_ARB_CONFIG_WORDS]; 147 }; 148 #endif 149