1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _PINMUX_H_ 25 #define _PINMUX_H_ 26 27 /* 28 * Pin groups which we adjust. There are three basic attributes of each pin 29 * group which use this enum: 30 * 31 * - function 32 * - pullup / pulldown 33 * - tristate or normal 34 */ 35 enum pmux_pingrp { 36 /* APB_MISC_PP_TRISTATE_REG_A_0 */ 37 PINGRP_ATA, 38 PINGRP_ATB, 39 PINGRP_ATC, 40 PINGRP_ATD, 41 PINGRP_CDEV1, 42 PINGRP_CDEV2, 43 PINGRP_CSUS, 44 PINGRP_DAP1, 45 46 PINGRP_DAP2, 47 PINGRP_DAP3, 48 PINGRP_DAP4, 49 PINGRP_DTA, 50 PINGRP_DTB, 51 PINGRP_DTC, 52 PINGRP_DTD, 53 PINGRP_DTE, 54 55 PINGRP_GPU, 56 PINGRP_GPV, 57 PINGRP_I2CP, 58 PINGRP_IRTX, 59 PINGRP_IRRX, 60 PINGRP_KBCB, 61 PINGRP_KBCA, 62 PINGRP_PMC, 63 64 PINGRP_PTA, 65 PINGRP_RM, 66 PINGRP_KBCE, 67 PINGRP_KBCF, 68 PINGRP_GMA, 69 PINGRP_GMC, 70 PINGRP_SDIO1, 71 PINGRP_OWC, 72 73 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ 74 PINGRP_GME, 75 PINGRP_SDC, 76 PINGRP_SDD, 77 PINGRP_RESERVED0, 78 PINGRP_SLXA, 79 PINGRP_SLXC, 80 PINGRP_SLXD, 81 PINGRP_SLXK, 82 83 PINGRP_SPDI, 84 PINGRP_SPDO, 85 PINGRP_SPIA, 86 PINGRP_SPIB, 87 PINGRP_SPIC, 88 PINGRP_SPID, 89 PINGRP_SPIE, 90 PINGRP_SPIF, 91 92 PINGRP_SPIG, 93 PINGRP_SPIH, 94 PINGRP_UAA, 95 PINGRP_UAB, 96 PINGRP_UAC, 97 PINGRP_UAD, 98 PINGRP_UCA, 99 PINGRP_UCB, 100 101 PINGRP_RESERVED1, 102 PINGRP_ATE, 103 PINGRP_KBCC, 104 PINGRP_RESERVED2, 105 PINGRP_RESERVED3, 106 PINGRP_GMB, 107 PINGRP_GMD, 108 PINGRP_DDC, 109 110 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ 111 PINGRP_LD0, 112 PINGRP_LD1, 113 PINGRP_LD2, 114 PINGRP_LD3, 115 PINGRP_LD4, 116 PINGRP_LD5, 117 PINGRP_LD6, 118 PINGRP_LD7, 119 120 PINGRP_LD8, 121 PINGRP_LD9, 122 PINGRP_LD10, 123 PINGRP_LD11, 124 PINGRP_LD12, 125 PINGRP_LD13, 126 PINGRP_LD14, 127 PINGRP_LD15, 128 129 PINGRP_LD16, 130 PINGRP_LD17, 131 PINGRP_LHP0, 132 PINGRP_LHP1, 133 PINGRP_LHP2, 134 PINGRP_LVP0, 135 PINGRP_LVP1, 136 PINGRP_HDINT, 137 138 PINGRP_LM0, 139 PINGRP_LM1, 140 PINGRP_LVS, 141 PINGRP_LSC0, 142 PINGRP_LSC1, 143 PINGRP_LSCK, 144 PINGRP_LDC, 145 PINGRP_LCSN, 146 147 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ 148 PINGRP_LSPI, 149 PINGRP_LSDA, 150 PINGRP_LSDI, 151 PINGRP_LPW0, 152 PINGRP_LPW1, 153 PINGRP_LPW2, 154 PINGRP_LDI, 155 PINGRP_LHS, 156 157 PINGRP_LPP, 158 PINGRP_RESERVED4, 159 PINGRP_KBCD, 160 PINGRP_GPU7, 161 PINGRP_DTF, 162 PINGRP_UDA, 163 PINGRP_CRTP, 164 PINGRP_SDB, 165 166 /* these pin groups only have pullup and pull down control */ 167 PINGRP_FIRST_NO_MUX, 168 PINGRP_CK32 = PINGRP_FIRST_NO_MUX, 169 PINGRP_DDRC, 170 PINGRP_PMCA, 171 PINGRP_PMCB, 172 PINGRP_PMCC, 173 PINGRP_PMCD, 174 PINGRP_PMCE, 175 PINGRP_XM2C, 176 PINGRP_XM2D, 177 178 PINGRP_COUNT, 179 }; 180 181 /* 182 * Functions which can be assigned to each of the pin groups. The values here 183 * bear no relation to the values programmed into pinmux registers and are 184 * purely a convenience. The translation is done through a table search. 185 */ 186 enum pmux_func { 187 PMUX_FUNC_AHB_CLK, 188 PMUX_FUNC_APB_CLK, 189 PMUX_FUNC_AUDIO_SYNC, 190 PMUX_FUNC_CRT, 191 PMUX_FUNC_DAP1, 192 PMUX_FUNC_DAP2, 193 PMUX_FUNC_DAP3, 194 PMUX_FUNC_DAP4, 195 PMUX_FUNC_DAP5, 196 PMUX_FUNC_DISPA, 197 PMUX_FUNC_DISPB, 198 PMUX_FUNC_EMC_TEST0_DLL, 199 PMUX_FUNC_EMC_TEST1_DLL, 200 PMUX_FUNC_GMI, 201 PMUX_FUNC_GMI_INT, 202 PMUX_FUNC_HDMI, 203 PMUX_FUNC_I2C, 204 PMUX_FUNC_I2C2, 205 PMUX_FUNC_I2C3, 206 PMUX_FUNC_IDE, 207 PMUX_FUNC_IRDA, 208 PMUX_FUNC_KBC, 209 PMUX_FUNC_MIO, 210 PMUX_FUNC_MIPI_HS, 211 PMUX_FUNC_NAND, 212 PMUX_FUNC_OSC, 213 PMUX_FUNC_OWR, 214 PMUX_FUNC_PCIE, 215 PMUX_FUNC_PLLA_OUT, 216 PMUX_FUNC_PLLC_OUT1, 217 PMUX_FUNC_PLLM_OUT1, 218 PMUX_FUNC_PLLP_OUT2, 219 PMUX_FUNC_PLLP_OUT3, 220 PMUX_FUNC_PLLP_OUT4, 221 PMUX_FUNC_PWM, 222 PMUX_FUNC_PWR_INTR, 223 PMUX_FUNC_PWR_ON, 224 PMUX_FUNC_RTCK, 225 PMUX_FUNC_SDIO1, 226 PMUX_FUNC_SDIO2, 227 PMUX_FUNC_SDIO3, 228 PMUX_FUNC_SDIO4, 229 PMUX_FUNC_SFLASH, 230 PMUX_FUNC_SPDIF, 231 PMUX_FUNC_SPI1, 232 PMUX_FUNC_SPI2, 233 PMUX_FUNC_SPI2_ALT, 234 PMUX_FUNC_SPI3, 235 PMUX_FUNC_SPI4, 236 PMUX_FUNC_TRACE, 237 PMUX_FUNC_TWC, 238 PMUX_FUNC_UARTA, 239 PMUX_FUNC_UARTB, 240 PMUX_FUNC_UARTC, 241 PMUX_FUNC_UARTD, 242 PMUX_FUNC_UARTE, 243 PMUX_FUNC_ULPI, 244 PMUX_FUNC_VI, 245 PMUX_FUNC_VI_SENSOR_CLK, 246 PMUX_FUNC_XIO, 247 PMUX_FUNC_SAFE, 248 249 /* These don't have a name, but can be used in the table */ 250 PMUX_FUNC_RSVD1, 251 PMUX_FUNC_RSVD2, 252 PMUX_FUNC_RSVD3, 253 PMUX_FUNC_RSVD4, 254 PMUX_FUNC_RSVD, /* Not valid and should not be used */ 255 256 PMUX_FUNC_COUNT, 257 258 PMUX_FUNC_NONE = -1, 259 }; 260 261 /* return 1 if a pmux_func is in range */ 262 #define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ 263 (func) != PMUX_FUNC_RSVD) 264 265 /* The pullup/pulldown state of a pin group */ 266 enum pmux_pull { 267 PMUX_PULL_NORMAL = 0, 268 PMUX_PULL_DOWN, 269 PMUX_PULL_UP, 270 }; 271 272 /* Defines whether a pin group is tristated or in normal operation */ 273 enum pmux_tristate { 274 PMUX_TRI_NORMAL = 0, 275 PMUX_TRI_TRISTATE = 1, 276 }; 277 278 /* Available power domains used by pin groups */ 279 enum pmux_vddio { 280 PMUX_VDDIO_BB = 0, 281 PMUX_VDDIO_LCD, 282 PMUX_VDDIO_VI, 283 PMUX_VDDIO_UART, 284 PMUX_VDDIO_DDR, 285 PMUX_VDDIO_NAND, 286 PMUX_VDDIO_SYS, 287 PMUX_VDDIO_AUDIO, 288 PMUX_VDDIO_SD, 289 290 PMUX_VDDIO_NONE 291 }; 292 293 enum { 294 PMUX_TRISTATE_REGS = 4, 295 PMUX_MUX_REGS = 7, 296 PMUX_PULL_REGS = 5, 297 }; 298 299 /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ 300 struct pmux_tri_ctlr { 301 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ 302 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ 303 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ 304 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ 305 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ 306 uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ 307 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ 308 309 uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ 310 311 uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ 312 uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ 313 uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ 314 }; 315 316 /* 317 * This defines the configuration for a pin, including the function assigned, 318 * pull up/down settings and tristate settings. Having set up one of these 319 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 320 * available is pinmux_config_table() to configure a list of pins. 321 */ 322 struct pingroup_config { 323 enum pmux_pingrp pingroup; /* pin group PINGRP_... */ 324 enum pmux_func func; /* function to assign FUNC_... */ 325 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ 326 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ 327 }; 328 329 /* Set a pin group to tristate */ 330 void pinmux_tristate_enable(enum pmux_pingrp pin); 331 332 /* Set a pin group to normal (non tristate) */ 333 void pinmux_tristate_disable(enum pmux_pingrp pin); 334 335 /* Set the pull up/down feature for a pin group */ 336 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 337 338 /* Set the mux function for a pin group */ 339 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 340 341 /* Set the complete configuration for a pin group */ 342 void pinmux_config_pingroup(struct pingroup_config *config); 343 344 void pinmux_set_tristate(enum pmux_pingrp pin, int enable); 345 346 /** 347 * Configuure a list of pin groups 348 * 349 * @param config List of config items 350 * @param len Number of config items in list 351 */ 352 void pinmux_config_table(struct pingroup_config *config, int len); 353 354 #endif /* PINMUX_H */ 355