1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PINMUX_H_ 9 #define _PINMUX_H_ 10 11 /* 12 * Pin groups which we adjust. There are three basic attributes of each pin 13 * group which use this enum: 14 * 15 * - function 16 * - pullup / pulldown 17 * - tristate or normal 18 */ 19 enum pmux_pingrp { 20 /* APB_MISC_PP_TRISTATE_REG_A_0 */ 21 PINGRP_ATA, 22 PINGRP_ATB, 23 PINGRP_ATC, 24 PINGRP_ATD, 25 PINGRP_CDEV1, 26 PINGRP_CDEV2, 27 PINGRP_CSUS, 28 PINGRP_DAP1, 29 30 PINGRP_DAP2, 31 PINGRP_DAP3, 32 PINGRP_DAP4, 33 PINGRP_DTA, 34 PINGRP_DTB, 35 PINGRP_DTC, 36 PINGRP_DTD, 37 PINGRP_DTE, 38 39 PINGRP_GPU, 40 PINGRP_GPV, 41 PINGRP_I2CP, 42 PINGRP_IRTX, 43 PINGRP_IRRX, 44 PINGRP_KBCB, 45 PINGRP_KBCA, 46 PINGRP_PMC, 47 48 PINGRP_PTA, 49 PINGRP_RM, 50 PINGRP_KBCE, 51 PINGRP_KBCF, 52 PINGRP_GMA, 53 PINGRP_GMC, 54 PINGRP_SDIO1, 55 PINGRP_OWC, 56 57 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ 58 PINGRP_GME, 59 PINGRP_SDC, 60 PINGRP_SDD, 61 PINGRP_RESERVED0, 62 PINGRP_SLXA, 63 PINGRP_SLXC, 64 PINGRP_SLXD, 65 PINGRP_SLXK, 66 67 PINGRP_SPDI, 68 PINGRP_SPDO, 69 PINGRP_SPIA, 70 PINGRP_SPIB, 71 PINGRP_SPIC, 72 PINGRP_SPID, 73 PINGRP_SPIE, 74 PINGRP_SPIF, 75 76 PINGRP_SPIG, 77 PINGRP_SPIH, 78 PINGRP_UAA, 79 PINGRP_UAB, 80 PINGRP_UAC, 81 PINGRP_UAD, 82 PINGRP_UCA, 83 PINGRP_UCB, 84 85 PINGRP_RESERVED1, 86 PINGRP_ATE, 87 PINGRP_KBCC, 88 PINGRP_RESERVED2, 89 PINGRP_RESERVED3, 90 PINGRP_GMB, 91 PINGRP_GMD, 92 PINGRP_DDC, 93 94 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ 95 PINGRP_LD0, 96 PINGRP_LD1, 97 PINGRP_LD2, 98 PINGRP_LD3, 99 PINGRP_LD4, 100 PINGRP_LD5, 101 PINGRP_LD6, 102 PINGRP_LD7, 103 104 PINGRP_LD8, 105 PINGRP_LD9, 106 PINGRP_LD10, 107 PINGRP_LD11, 108 PINGRP_LD12, 109 PINGRP_LD13, 110 PINGRP_LD14, 111 PINGRP_LD15, 112 113 PINGRP_LD16, 114 PINGRP_LD17, 115 PINGRP_LHP0, 116 PINGRP_LHP1, 117 PINGRP_LHP2, 118 PINGRP_LVP0, 119 PINGRP_LVP1, 120 PINGRP_HDINT, 121 122 PINGRP_LM0, 123 PINGRP_LM1, 124 PINGRP_LVS, 125 PINGRP_LSC0, 126 PINGRP_LSC1, 127 PINGRP_LSCK, 128 PINGRP_LDC, 129 PINGRP_LCSN, 130 131 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ 132 PINGRP_LSPI, 133 PINGRP_LSDA, 134 PINGRP_LSDI, 135 PINGRP_LPW0, 136 PINGRP_LPW1, 137 PINGRP_LPW2, 138 PINGRP_LDI, 139 PINGRP_LHS, 140 141 PINGRP_LPP, 142 PINGRP_RESERVED4, 143 PINGRP_KBCD, 144 PINGRP_GPU7, 145 PINGRP_DTF, 146 PINGRP_UDA, 147 PINGRP_CRTP, 148 PINGRP_SDB, 149 150 /* these pin groups only have pullup and pull down control */ 151 PINGRP_FIRST_NO_MUX, 152 PINGRP_CK32 = PINGRP_FIRST_NO_MUX, 153 PINGRP_DDRC, 154 PINGRP_PMCA, 155 PINGRP_PMCB, 156 PINGRP_PMCC, 157 PINGRP_PMCD, 158 PINGRP_PMCE, 159 PINGRP_XM2C, 160 PINGRP_XM2D, 161 162 PINGRP_COUNT, 163 }; 164 165 /* 166 * Functions which can be assigned to each of the pin groups. The values here 167 * bear no relation to the values programmed into pinmux registers and are 168 * purely a convenience. The translation is done through a table search. 169 */ 170 enum pmux_func { 171 PMUX_FUNC_AHB_CLK, 172 PMUX_FUNC_APB_CLK, 173 PMUX_FUNC_AUDIO_SYNC, 174 PMUX_FUNC_CRT, 175 PMUX_FUNC_DAP1, 176 PMUX_FUNC_DAP2, 177 PMUX_FUNC_DAP3, 178 PMUX_FUNC_DAP4, 179 PMUX_FUNC_DAP5, 180 PMUX_FUNC_DISPA, 181 PMUX_FUNC_DISPB, 182 PMUX_FUNC_EMC_TEST0_DLL, 183 PMUX_FUNC_EMC_TEST1_DLL, 184 PMUX_FUNC_GMI, 185 PMUX_FUNC_GMI_INT, 186 PMUX_FUNC_HDMI, 187 PMUX_FUNC_I2C, 188 PMUX_FUNC_I2C2, 189 PMUX_FUNC_I2C3, 190 PMUX_FUNC_IDE, 191 PMUX_FUNC_KBC, 192 PMUX_FUNC_MIO, 193 PMUX_FUNC_MIPI_HS, 194 PMUX_FUNC_NAND, 195 PMUX_FUNC_OSC, 196 PMUX_FUNC_OWR, 197 PMUX_FUNC_PCIE, 198 PMUX_FUNC_PLLA_OUT, 199 PMUX_FUNC_PLLC_OUT1, 200 PMUX_FUNC_PLLM_OUT1, 201 PMUX_FUNC_PLLP_OUT2, 202 PMUX_FUNC_PLLP_OUT3, 203 PMUX_FUNC_PLLP_OUT4, 204 PMUX_FUNC_PWM, 205 PMUX_FUNC_PWR_INTR, 206 PMUX_FUNC_PWR_ON, 207 PMUX_FUNC_RTCK, 208 PMUX_FUNC_SDIO1, 209 PMUX_FUNC_SDIO2, 210 PMUX_FUNC_SDIO3, 211 PMUX_FUNC_SDIO4, 212 PMUX_FUNC_SFLASH, 213 PMUX_FUNC_SPDIF, 214 PMUX_FUNC_SPI1, 215 PMUX_FUNC_SPI2, 216 PMUX_FUNC_SPI2_ALT, 217 PMUX_FUNC_SPI3, 218 PMUX_FUNC_SPI4, 219 PMUX_FUNC_TRACE, 220 PMUX_FUNC_TWC, 221 PMUX_FUNC_UARTA, 222 PMUX_FUNC_UARTB, 223 PMUX_FUNC_UARTC, 224 PMUX_FUNC_UARTD, 225 PMUX_FUNC_UARTE, 226 PMUX_FUNC_ULPI, 227 PMUX_FUNC_VI, 228 PMUX_FUNC_VI_SENSOR_CLK, 229 PMUX_FUNC_XIO, 230 PMUX_FUNC_SAFE, 231 232 /* These don't have a name, but can be used in the table */ 233 PMUX_FUNC_RSVD1, 234 PMUX_FUNC_RSVD2, 235 PMUX_FUNC_RSVD3, 236 PMUX_FUNC_RSVD4, 237 PMUX_FUNC_RSVD, /* Not valid and should not be used */ 238 239 PMUX_FUNC_COUNT, 240 241 PMUX_FUNC_NONE = -1, 242 }; 243 244 /* return 1 if a pmux_func is in range */ 245 #define pmux_func_isvalid(func) ((func) >= 0 && (func) < PMUX_FUNC_COUNT && \ 246 (func) != PMUX_FUNC_RSVD) 247 248 /* The pullup/pulldown state of a pin group */ 249 enum pmux_pull { 250 PMUX_PULL_NORMAL = 0, 251 PMUX_PULL_DOWN, 252 PMUX_PULL_UP, 253 }; 254 255 /* Defines whether a pin group is tristated or in normal operation */ 256 enum pmux_tristate { 257 PMUX_TRI_NORMAL = 0, 258 PMUX_TRI_TRISTATE = 1, 259 }; 260 261 /* Available power domains used by pin groups */ 262 enum pmux_vddio { 263 PMUX_VDDIO_BB = 0, 264 PMUX_VDDIO_LCD, 265 PMUX_VDDIO_VI, 266 PMUX_VDDIO_UART, 267 PMUX_VDDIO_DDR, 268 PMUX_VDDIO_NAND, 269 PMUX_VDDIO_SYS, 270 PMUX_VDDIO_AUDIO, 271 PMUX_VDDIO_SD, 272 273 PMUX_VDDIO_NONE 274 }; 275 276 enum { 277 PMUX_TRISTATE_REGS = 4, 278 PMUX_MUX_REGS = 7, 279 PMUX_PULL_REGS = 5, 280 }; 281 282 /* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */ 283 struct pmux_tri_ctlr { 284 uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */ 285 uint pmt_reserved1; /* ABP_MISC_PP_ reserved offset 04 */ 286 uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ 287 uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */ 288 uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */ 289 uint pmt_tri[PMUX_TRISTATE_REGS];/* _TRI_STATE_REG_A/B/C/D_0 14-20 */ 290 uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */ 291 292 uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ 293 294 uint pmt_ctl[PMUX_MUX_REGS]; /* _PIN_MUX_CTL_A-G_0, offset 80 */ 295 uint pmt_reserved4; /* ABP_MISC_PP_ reserved offset 9c */ 296 uint pmt_pull[PMUX_PULL_REGS]; /* APB_MISC_PP_PULLUPDOWN_REG_A-E */ 297 }; 298 299 /* 300 * This defines the configuration for a pin, including the function assigned, 301 * pull up/down settings and tristate settings. Having set up one of these 302 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 303 * available is pinmux_config_table() to configure a list of pins. 304 */ 305 struct pingroup_config { 306 enum pmux_pingrp pingroup; /* pin group PINGRP_... */ 307 enum pmux_func func; /* function to assign FUNC_... */ 308 enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/ 309 enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */ 310 }; 311 312 /* Set a pin group to tristate */ 313 void pinmux_tristate_enable(enum pmux_pingrp pin); 314 315 /* Set a pin group to normal (non tristate) */ 316 void pinmux_tristate_disable(enum pmux_pingrp pin); 317 318 /* Set the pull up/down feature for a pin group */ 319 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 320 321 /* Set the mux function for a pin group */ 322 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 323 324 /* Set the complete configuration for a pin group */ 325 void pinmux_config_pingroup(const struct pingroup_config *config); 326 327 void pinmux_set_tristate(enum pmux_pingrp pin, int enable); 328 329 /** 330 * Configuure a list of pin groups 331 * 332 * @param config List of config items 333 * @param len Number of config items in list 334 */ 335 void pinmux_config_table(const struct pingroup_config *config, int len); 336 337 #endif /* PINMUX_H */ 338