1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA20_PINMUX_H_ 9 #define _TEGRA20_PINMUX_H_ 10 11 /* 12 * Pin groups which we adjust. There are three basic attributes of each pin 13 * group which use this enum: 14 * 15 * - function 16 * - pullup / pulldown 17 * - tristate or normal 18 */ 19 enum pmux_pingrp { 20 /* APB_MISC_PP_TRISTATE_REG_A_0 */ 21 PMUX_PINGRP_ATA, 22 PMUX_PINGRP_ATB, 23 PMUX_PINGRP_ATC, 24 PMUX_PINGRP_ATD, 25 PMUX_PINGRP_CDEV1, 26 PMUX_PINGRP_CDEV2, 27 PMUX_PINGRP_CSUS, 28 PMUX_PINGRP_DAP1, 29 30 PMUX_PINGRP_DAP2, 31 PMUX_PINGRP_DAP3, 32 PMUX_PINGRP_DAP4, 33 PMUX_PINGRP_DTA, 34 PMUX_PINGRP_DTB, 35 PMUX_PINGRP_DTC, 36 PMUX_PINGRP_DTD, 37 PMUX_PINGRP_DTE, 38 39 PMUX_PINGRP_GPU, 40 PMUX_PINGRP_GPV, 41 PMUX_PINGRP_I2CP, 42 PMUX_PINGRP_IRTX, 43 PMUX_PINGRP_IRRX, 44 PMUX_PINGRP_KBCB, 45 PMUX_PINGRP_KBCA, 46 PMUX_PINGRP_PMC, 47 48 PMUX_PINGRP_PTA, 49 PMUX_PINGRP_RM, 50 PMUX_PINGRP_KBCE, 51 PMUX_PINGRP_KBCF, 52 PMUX_PINGRP_GMA, 53 PMUX_PINGRP_GMC, 54 PMUX_PINGRP_SDIO1, 55 PMUX_PINGRP_OWC, 56 57 /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ 58 PMUX_PINGRP_GME, 59 PMUX_PINGRP_SDC, 60 PMUX_PINGRP_SDD, 61 PMUX_PINGRP_RESERVED0, 62 PMUX_PINGRP_SLXA, 63 PMUX_PINGRP_SLXC, 64 PMUX_PINGRP_SLXD, 65 PMUX_PINGRP_SLXK, 66 67 PMUX_PINGRP_SPDI, 68 PMUX_PINGRP_SPDO, 69 PMUX_PINGRP_SPIA, 70 PMUX_PINGRP_SPIB, 71 PMUX_PINGRP_SPIC, 72 PMUX_PINGRP_SPID, 73 PMUX_PINGRP_SPIE, 74 PMUX_PINGRP_SPIF, 75 76 PMUX_PINGRP_SPIG, 77 PMUX_PINGRP_SPIH, 78 PMUX_PINGRP_UAA, 79 PMUX_PINGRP_UAB, 80 PMUX_PINGRP_UAC, 81 PMUX_PINGRP_UAD, 82 PMUX_PINGRP_UCA, 83 PMUX_PINGRP_UCB, 84 85 PMUX_PINGRP_RESERVED1, 86 PMUX_PINGRP_ATE, 87 PMUX_PINGRP_KBCC, 88 PMUX_PINGRP_RESERVED2, 89 PMUX_PINGRP_RESERVED3, 90 PMUX_PINGRP_GMB, 91 PMUX_PINGRP_GMD, 92 PMUX_PINGRP_DDC, 93 94 /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ 95 PMUX_PINGRP_LD0, 96 PMUX_PINGRP_LD1, 97 PMUX_PINGRP_LD2, 98 PMUX_PINGRP_LD3, 99 PMUX_PINGRP_LD4, 100 PMUX_PINGRP_LD5, 101 PMUX_PINGRP_LD6, 102 PMUX_PINGRP_LD7, 103 104 PMUX_PINGRP_LD8, 105 PMUX_PINGRP_LD9, 106 PMUX_PINGRP_LD10, 107 PMUX_PINGRP_LD11, 108 PMUX_PINGRP_LD12, 109 PMUX_PINGRP_LD13, 110 PMUX_PINGRP_LD14, 111 PMUX_PINGRP_LD15, 112 113 PMUX_PINGRP_LD16, 114 PMUX_PINGRP_LD17, 115 PMUX_PINGRP_LHP0, 116 PMUX_PINGRP_LHP1, 117 PMUX_PINGRP_LHP2, 118 PMUX_PINGRP_LVP0, 119 PMUX_PINGRP_LVP1, 120 PMUX_PINGRP_HDINT, 121 122 PMUX_PINGRP_LM0, 123 PMUX_PINGRP_LM1, 124 PMUX_PINGRP_LVS, 125 PMUX_PINGRP_LSC0, 126 PMUX_PINGRP_LSC1, 127 PMUX_PINGRP_LSCK, 128 PMUX_PINGRP_LDC, 129 PMUX_PINGRP_LCSN, 130 131 /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ 132 PMUX_PINGRP_LSPI, 133 PMUX_PINGRP_LSDA, 134 PMUX_PINGRP_LSDI, 135 PMUX_PINGRP_LPW0, 136 PMUX_PINGRP_LPW1, 137 PMUX_PINGRP_LPW2, 138 PMUX_PINGRP_LDI, 139 PMUX_PINGRP_LHS, 140 141 PMUX_PINGRP_LPP, 142 PMUX_PINGRP_RESERVED4, 143 PMUX_PINGRP_KBCD, 144 PMUX_PINGRP_GPU7, 145 PMUX_PINGRP_DTF, 146 PMUX_PINGRP_UDA, 147 PMUX_PINGRP_CRTP, 148 PMUX_PINGRP_SDB, 149 150 /* these pin groups only have pullup and pull down control */ 151 PMUX_PINGRP_CK32, 152 PMUX_PINGRP_DDRC, 153 PMUX_PINGRP_PMCA, 154 PMUX_PINGRP_PMCB, 155 PMUX_PINGRP_PMCC, 156 PMUX_PINGRP_PMCD, 157 PMUX_PINGRP_PMCE, 158 PMUX_PINGRP_XM2C, 159 PMUX_PINGRP_XM2D, 160 PMUX_PINGRP_COUNT, 161 }; 162 163 /* 164 * Functions which can be assigned to each of the pin groups. The values here 165 * bear no relation to the values programmed into pinmux registers and are 166 * purely a convenience. The translation is done through a table search. 167 */ 168 enum pmux_func { 169 PMUX_FUNC_DEFAULT, 170 PMUX_FUNC_AHB_CLK, 171 PMUX_FUNC_APB_CLK, 172 PMUX_FUNC_AUDIO_SYNC, 173 PMUX_FUNC_CRT, 174 PMUX_FUNC_DAP1, 175 PMUX_FUNC_DAP2, 176 PMUX_FUNC_DAP3, 177 PMUX_FUNC_DAP4, 178 PMUX_FUNC_DAP5, 179 PMUX_FUNC_DISPA, 180 PMUX_FUNC_DISPB, 181 PMUX_FUNC_EMC_TEST0_DLL, 182 PMUX_FUNC_EMC_TEST1_DLL, 183 PMUX_FUNC_GMI, 184 PMUX_FUNC_GMI_INT, 185 PMUX_FUNC_HDMI, 186 PMUX_FUNC_I2C, 187 PMUX_FUNC_I2C2, 188 PMUX_FUNC_I2C3, 189 PMUX_FUNC_IDE, 190 PMUX_FUNC_KBC, 191 PMUX_FUNC_MIO, 192 PMUX_FUNC_MIPI_HS, 193 PMUX_FUNC_NAND, 194 PMUX_FUNC_OSC, 195 PMUX_FUNC_OWR, 196 PMUX_FUNC_PCIE, 197 PMUX_FUNC_PLLA_OUT, 198 PMUX_FUNC_PLLC_OUT1, 199 PMUX_FUNC_PLLM_OUT1, 200 PMUX_FUNC_PLLP_OUT2, 201 PMUX_FUNC_PLLP_OUT3, 202 PMUX_FUNC_PLLP_OUT4, 203 PMUX_FUNC_PWM, 204 PMUX_FUNC_PWR_INTR, 205 PMUX_FUNC_PWR_ON, 206 PMUX_FUNC_RTCK, 207 PMUX_FUNC_SDIO1, 208 PMUX_FUNC_SDIO2, 209 PMUX_FUNC_SDIO3, 210 PMUX_FUNC_SDIO4, 211 PMUX_FUNC_SFLASH, 212 PMUX_FUNC_SPDIF, 213 PMUX_FUNC_SPI1, 214 PMUX_FUNC_SPI2, 215 PMUX_FUNC_SPI2_ALT, 216 PMUX_FUNC_SPI3, 217 PMUX_FUNC_SPI4, 218 PMUX_FUNC_TRACE, 219 PMUX_FUNC_TWC, 220 PMUX_FUNC_UARTA, 221 PMUX_FUNC_UARTB, 222 PMUX_FUNC_UARTC, 223 PMUX_FUNC_UARTD, 224 PMUX_FUNC_UARTE, 225 PMUX_FUNC_ULPI, 226 PMUX_FUNC_VI, 227 PMUX_FUNC_VI_SENSOR_CLK, 228 PMUX_FUNC_XIO, 229 PMUX_FUNC_RSVD1, 230 PMUX_FUNC_RSVD2, 231 PMUX_FUNC_RSVD3, 232 PMUX_FUNC_RSVD4, 233 PMUX_FUNC_COUNT, 234 }; 235 236 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868 237 #include <asm/arch-tegra/pinmux.h> 238 239 #endif /* _TEGRA20_PINMUX_H_ */ 240