1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _GP_PADCTRL_H_ 25 #define _GP_PADCTRL_H_ 26 27 /* APB_MISC_GP and padctrl registers */ 28 struct apb_misc_gp_ctlr { 29 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 30 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 31 u32 reserved0[22]; /* 0x08 - 0x5C: */ 32 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 33 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 34 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 35 u32 aocfg2; /* 0x6c: APB_MISC_GP_AOCFG2PADCTRL */ 36 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 37 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 38 u32 cdevcfg1; /* 0x78: APB_MISC_GP_CDEV1CFGPADCTRL */ 39 u32 cdevcfg2; /* 0x7C: APB_MISC_GP_CDEV2CFGPADCTRL */ 40 u32 csuscfg; /* 0x80: APB_MISC_GP_CSUSCFGPADCTRL */ 41 u32 dap1cfg; /* 0x84: APB_MISC_GP_DAP1CFGPADCTRL */ 42 u32 dap2cfg; /* 0x88: APB_MISC_GP_DAP2CFGPADCTRL */ 43 u32 dap3cfg; /* 0x8C: APB_MISC_GP_DAP3CFGPADCTRL */ 44 u32 dap4cfg; /* 0x90: APB_MISC_GP_DAP4CFGPADCTRL */ 45 u32 dbgcfg; /* 0x94: APB_MISC_GP_DBGCFGPADCTRL */ 46 u32 lcdcfg1; /* 0x98: APB_MISC_GP_LCDCFG1PADCTRL */ 47 u32 lcdcfg2; /* 0x9C: APB_MISC_GP_LCDCFG2PADCTRL */ 48 u32 sdmmc2_cfg; /* 0xA0: APB_MISC_GP_SDMMC2CFGPADCTRL */ 49 u32 sdmmc3_cfg; /* 0xA4: APB_MISC_GP_SDMMC3CFGPADCTRL */ 50 u32 spicfg; /* 0xA8: APB_MISC_GP_SPICFGPADCTRL */ 51 u32 uaacfg; /* 0xAC: APB_MISC_GP_UAACFGPADCTRL */ 52 u32 uabcfg; /* 0xB0: APB_MISC_GP_UABCFGPADCTRL */ 53 u32 uart2cfg; /* 0xB4: APB_MISC_GP_UART2CFGPADCTRL */ 54 u32 uart3cfg; /* 0xB8: APB_MISC_GP_UART3CFGPADCTRL */ 55 u32 vicfg1; /* 0xBC: APB_MISC_GP_VICFG1PADCTRL */ 56 u32 vicfg2; /* 0xC0: APB_MISC_GP_VICFG2PADCTRL */ 57 u32 xm2cfga; /* 0xC4: APB_MISC_GP_XM2CFGAPADCTRL */ 58 u32 xm2cfgc; /* 0xC8: APB_MISC_GP_XM2CFGCPADCTRL */ 59 u32 xm2cfgd; /* 0xCC: APB_MISC_GP_XM2CFGDPADCTRL */ 60 u32 xm2clkcfg; /* 0xD0: APB_MISC_GP_XM2CLKCFGPADCTRL */ 61 u32 memcomp; /* 0xD4: APB_MISC_GP_MEMCOMPPADCTRL */ 62 }; 63 64 /* bit fields definitions for APB_MISC_GP_HIDREV register */ 65 #define HIDREV_CHIPID_SHIFT 8 66 #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) 67 #define HIDREV_MAJORPREV_SHIFT 4 68 #define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) 69 70 /* CHIPID field returned from APB_MISC_GP_HIDREV register */ 71 #define CHIPID_TEGRA20 0x20 72 73 #endif 74