1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _ARCH_EMC_H_ 25 #define _ARCH_EMC_H_ 26 27 #include <asm/types.h> 28 29 #define TEGRA_EMC_NUM_REGS 46 30 31 /* EMC Registers */ 32 struct emc_ctlr { 33 u32 cfg; /* 0x00: EMC_CFG */ 34 u32 reserved0[3]; /* 0x04 ~ 0x0C */ 35 u32 adr_cfg; /* 0x10: EMC_ADR_CFG */ 36 u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */ 37 u32 reserved1[2]; /* 0x18 ~ 0x18 */ 38 u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */ 39 u32 pin; /* 0x24: EMC_PIN */ 40 u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */ 41 u32 rc; /* 0x2C: EMC_RC */ 42 u32 rfc; /* 0x30: EMC_RFC */ 43 u32 ras; /* 0x34: EMC_RAS */ 44 u32 rp; /* 0x38: EMC_RP */ 45 u32 r2w; /* 0x3C: EMC_R2W */ 46 u32 w2r; /* 0x40: EMC_W2R */ 47 u32 r2p; /* 0x44: EMC_R2P */ 48 u32 w2p; /* 0x48: EMC_W2P */ 49 u32 rd_rcd; /* 0x4C: EMC_RD_RCD */ 50 u32 wd_rcd; /* 0x50: EMC_WD_RCD */ 51 u32 rrd; /* 0x54: EMC_RRD */ 52 u32 rext; /* 0x58: EMC_REXT */ 53 u32 wdv; /* 0x5C: EMC_WDV */ 54 u32 quse; /* 0x60: EMC_QUSE */ 55 u32 qrst; /* 0x64: EMC_QRST */ 56 u32 qsafe; /* 0x68: EMC_QSAFE */ 57 u32 rdv; /* 0x6C: EMC_RDV */ 58 u32 refresh; /* 0x70: EMC_REFRESH */ 59 u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */ 60 u32 pdex2wr; /* 0x78: EMC_PDEX2WR */ 61 u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */ 62 u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */ 63 u32 act2pden; /* 0x84: EMC_ACT2PDEN */ 64 u32 ar2pden; /* 0x88: EMC_AR2PDEN */ 65 u32 rw2pden; /* 0x8C: EMC_RW2PDEN */ 66 u32 txsr; /* 0x90: EMC_TXSR */ 67 u32 tcke; /* 0x94: EMC_TCKE */ 68 u32 tfaw; /* 0x98: EMC_TFAW */ 69 u32 trpab; /* 0x9C: EMC_TRPAB */ 70 u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */ 71 u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */ 72 u32 trefbw; /* 0xA8: EMC_TREFBW */ 73 u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */ 74 u32 odt_write; /* 0xB0: EMC_ODT_WRITE */ 75 u32 odt_read; /* 0xB4: EMC_ODT_READ */ 76 u32 reserved2[5]; /* 0xB8 ~ 0xC8 */ 77 u32 mrs; /* 0xCC: EMC_MRS */ 78 u32 emrs; /* 0xD0: EMC_EMRS */ 79 u32 ref; /* 0xD4: EMC_REF */ 80 u32 pre; /* 0xD8: EMC_PRE */ 81 u32 nop; /* 0xDC: EMC_NOP */ 82 u32 self_ref; /* 0xE0: EMC_SELF_REF */ 83 u32 dpd; /* 0xE4: EMC_DPD */ 84 u32 mrw; /* 0xE8: EMC_MRW */ 85 u32 mrr; /* 0xEC: EMC_MRR */ 86 u32 reserved3; /* 0xF0: */ 87 u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */ 88 u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */ 89 u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */ 90 u32 fbio_spare; /* 0x100: SBIO_SPARE */ 91 /* There are more registers ... */ 92 }; 93 94 /** 95 * Set up the EMC for the given rate. The timing parameters are retrieved 96 * from the device tree "nvidia,tegra20-emc" node and its 97 * "nvidia,tegra20-emc-table" sub-nodes. 98 * 99 * @param blob Device tree blob 100 * @param rate Clock speed of memory controller in Hz (=2x memory bus rate) 101 * @return 0 if ok, else -ve error code (look in emc.c to decode it) 102 */ 103 int tegra_set_emc(const void *blob, unsigned rate); 104 105 /** 106 * Get a pointer to the EMC controller from the device tree. 107 * 108 * @param blob Device tree blob 109 * @return pointer to EMC controller 110 */ 111 struct emc_ctlr *emc_get_controller(const void *blob); 112 113 #endif 114