1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2011 The Chromium OS Authors.
4  * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _ARCH_EMC_H_
8 #define _ARCH_EMC_H_
9 
10 #include <asm/types.h>
11 
12 #define TEGRA_EMC_NUM_REGS	46
13 
14 /* EMC Registers */
15 struct emc_ctlr {
16 	u32 cfg;		/* 0x00: EMC_CFG */
17 	u32 reserved0[3];	/* 0x04 ~ 0x0C */
18 	u32 adr_cfg;		/* 0x10: EMC_ADR_CFG */
19 	u32 adr_cfg1;		/* 0x14: EMC_ADR_CFG_1 */
20 	u32 reserved1[2];	/* 0x18 ~ 0x18 */
21 	u32 refresh_ctrl;	/* 0x20: EMC_REFCTRL */
22 	u32 pin;		/* 0x24: EMC_PIN */
23 	u32 timing_ctrl;	/* 0x28: EMC_TIMING_CONTROL */
24 	u32 rc;			/* 0x2C: EMC_RC */
25 	u32 rfc;		/* 0x30: EMC_RFC */
26 	u32 ras;		/* 0x34: EMC_RAS */
27 	u32 rp;			/* 0x38: EMC_RP */
28 	u32 r2w;		/* 0x3C: EMC_R2W */
29 	u32 w2r;		/* 0x40: EMC_W2R */
30 	u32 r2p;		/* 0x44: EMC_R2P */
31 	u32 w2p;		/* 0x48: EMC_W2P */
32 	u32 rd_rcd;		/* 0x4C: EMC_RD_RCD */
33 	u32 wd_rcd;		/* 0x50: EMC_WD_RCD */
34 	u32 rrd;		/* 0x54: EMC_RRD */
35 	u32 rext;		/* 0x58: EMC_REXT */
36 	u32 wdv;		/* 0x5C: EMC_WDV */
37 	u32 quse;		/* 0x60: EMC_QUSE */
38 	u32 qrst;		/* 0x64: EMC_QRST */
39 	u32 qsafe;		/* 0x68: EMC_QSAFE */
40 	u32 rdv;		/* 0x6C: EMC_RDV */
41 	u32 refresh;		/* 0x70: EMC_REFRESH */
42 	u32 burst_refresh_num;	/* 0x74: EMC_BURST_REFRESH_NUM */
43 	u32 pdex2wr;		/* 0x78: EMC_PDEX2WR */
44 	u32 pdex2rd;		/* 0x7c: EMC_PDEX2RD */
45 	u32 pchg2pden;		/* 0x80: EMC_PCHG2PDEN */
46 	u32 act2pden;		/* 0x84: EMC_ACT2PDEN */
47 	u32 ar2pden;		/* 0x88: EMC_AR2PDEN */
48 	u32 rw2pden;		/* 0x8C: EMC_RW2PDEN */
49 	u32 txsr;		/* 0x90: EMC_TXSR */
50 	u32 tcke;		/* 0x94: EMC_TCKE */
51 	u32 tfaw;		/* 0x98: EMC_TFAW */
52 	u32 trpab;		/* 0x9C: EMC_TRPAB */
53 	u32 tclkstable;		/* 0xA0: EMC_TCLKSTABLE */
54 	u32 tclkstop;		/* 0xA4: EMC_TCLKSTOP */
55 	u32 trefbw;		/* 0xA8: EMC_TREFBW */
56 	u32 quse_extra;		/* 0xAC: EMC_QUSE_EXTRA */
57 	u32 odt_write;		/* 0xB0: EMC_ODT_WRITE */
58 	u32 odt_read;		/* 0xB4: EMC_ODT_READ */
59 	u32 reserved2[5];	/* 0xB8 ~ 0xC8 */
60 	u32 mrs;		/* 0xCC: EMC_MRS */
61 	u32 emrs;		/* 0xD0: EMC_EMRS */
62 	u32 ref;		/* 0xD4: EMC_REF */
63 	u32 pre;		/* 0xD8: EMC_PRE */
64 	u32 nop;		/* 0xDC: EMC_NOP */
65 	u32 self_ref;		/* 0xE0: EMC_SELF_REF */
66 	u32 dpd;		/* 0xE4: EMC_DPD */
67 	u32 mrw;		/* 0xE8: EMC_MRW */
68 	u32 mrr;		/* 0xEC: EMC_MRR */
69 	u32 reserved3;		/* 0xF0: */
70 	u32 fbio_cfg1;		/* 0xF4: EMC_FBIO_CFG1 */
71 	u32 fbio_dqsib_dly;	/* 0xF8: EMC_FBIO_DQSIB_DLY */
72 	u32 fbio_dqsib_dly_msb;	/* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
73 	u32 fbio_spare;		/* 0x100: SBIO_SPARE */
74 				/* There are more registers ... */
75 };
76 
77 /**
78  * Set up the EMC for the given rate. The timing parameters are retrieved
79  * from the device tree "nvidia,tegra20-emc" node and its
80  * "nvidia,tegra20-emc-table" sub-nodes.
81  *
82  * @param blob	Device tree blob
83  * @param rate	Clock speed of memory controller in Hz (=2x memory bus rate)
84  * @return 0 if ok, else -ve error code (look in emc.c to decode it)
85  */
86 int tegra_set_emc(const void *blob, unsigned rate);
87 
88 /**
89  * Get a pointer to the EMC controller from the device tree.
90  *
91  * @param blob	Device tree blob
92  * @return pointer to EMC controller
93  */
94 struct emc_ctlr *emc_get_controller(const void *blob);
95 
96 #endif
97