1 /* 2 * (C) Copyright 2010 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef __ASM_ARCH_TEGRA_DISPLAY_H 25 #define __ASM_ARCH_TEGRA_DISPLAY_H 26 27 #include <asm/arch/dc.h> 28 #include <fdtdec.h> 29 30 /* This holds information about a window which can be displayed */ 31 struct disp_ctl_win { 32 enum win_color_depth_id fmt; /* Color depth/format */ 33 unsigned bpp; /* Bits per pixel */ 34 phys_addr_t phys_addr; /* Physical address in memory */ 35 unsigned x; /* Horizontal address offset (bytes) */ 36 unsigned y; /* Veritical address offset (bytes) */ 37 unsigned w; /* Width of source window */ 38 unsigned h; /* Height of source window */ 39 unsigned stride; /* Number of bytes per line */ 40 unsigned out_x; /* Left edge of output window (col) */ 41 unsigned out_y; /* Top edge of output window (row) */ 42 unsigned out_w; /* Width of output window in pixels */ 43 unsigned out_h; /* Height of output window in pixels */ 44 }; 45 46 #define FDT_LCD_TIMINGS 4 47 48 enum { 49 FDT_LCD_TIMING_REF_TO_SYNC, 50 FDT_LCD_TIMING_SYNC_WIDTH, 51 FDT_LCD_TIMING_BACK_PORCH, 52 FDT_LCD_TIMING_FRONT_PORCH, 53 54 FDT_LCD_TIMING_COUNT, 55 }; 56 57 enum lcd_cache_t { 58 FDT_LCD_CACHE_OFF = 0, 59 FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, 60 FDT_LCD_CACHE_WRITE_BACK = 1 << 1, 61 FDT_LCD_CACHE_FLUSH = 1 << 2, 62 FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | 63 FDT_LCD_CACHE_FLUSH, 64 }; 65 66 /* Information about the display controller */ 67 struct fdt_disp_config { 68 int valid; /* config is valid */ 69 int width; /* width in pixels */ 70 int height; /* height in pixels */ 71 int bpp; /* number of bits per pixel */ 72 73 /* 74 * log2 of number of bpp, in general, unless it bpp is 24 in which 75 * case this field holds 24 also! This is a U-Boot thing. 76 */ 77 int log2_bpp; 78 struct disp_ctlr *disp; /* Display controller to use */ 79 fdt_addr_t frame_buffer; /* Address of frame buffer */ 80 unsigned pixel_clock; /* Pixel clock in Hz */ 81 uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ 82 uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ 83 int panel_node; /* node offset of panel information */ 84 }; 85 86 /* Information about the LCD panel */ 87 struct fdt_panel_config { 88 int pwm_channel; /* PWM channel to use for backlight */ 89 enum lcd_cache_t cache_type; 90 91 struct fdt_gpio_state backlight_en; /* GPIO for backlight enable */ 92 struct fdt_gpio_state lvds_shutdown; /* GPIO for lvds shutdown */ 93 struct fdt_gpio_state backlight_vdd; /* GPIO for backlight vdd */ 94 struct fdt_gpio_state panel_vdd; /* GPIO for panel vdd */ 95 /* 96 * Panel required timings 97 * Timing 1: delay between panel_vdd-rise and data-rise 98 * Timing 2: delay between data-rise and backlight_vdd-rise 99 * Timing 3: delay between backlight_vdd and pwm-rise 100 * Timing 4: delay between pwm-rise and backlight_en-rise 101 */ 102 uint panel_timings[FDT_LCD_TIMINGS]; 103 }; 104 105 /** 106 * Register a new display based on device tree configuration. 107 * 108 * The frame buffer can be positioned by U-Boot or overriden by the fdt. 109 * You should pass in the U-Boot address here, and check the contents of 110 * struct fdt_disp_config to see what was actually chosen. 111 * 112 * @param blob Device tree blob 113 * @param default_lcd_base Default address of LCD frame buffer 114 * @return 0 if ok, -1 on error (unsupported bits per pixel) 115 */ 116 int tegra_display_probe(const void *blob, void *default_lcd_base); 117 118 /** 119 * Return the current display configuration 120 * 121 * @return pointer to display configuration, or NULL if there is no valid 122 * config 123 */ 124 struct fdt_disp_config *tegra_display_get_config(void); 125 126 /** 127 * Perform the next stage of the LCD init if it is time to do so. 128 * 129 * LCD init can be time-consuming because of the number of delays we need 130 * while waiting for the backlight power supply, etc. This function can 131 * be called at various times during U-Boot operation to advance the 132 * initialization of the LCD to the next stage if sufficient time has 133 * passed since the last stage. It keeps track of what stage it is up to 134 * and the time that it is permitted to move to the next stage. 135 * 136 * The final call should have wait=1 to complete the init. 137 * 138 * @param blob fdt blob containing LCD information 139 * @param wait 1 to wait until all init is complete, and then return 140 * 0 to return immediately, potentially doing nothing if it is 141 * not yet time for the next init. 142 */ 143 int tegra_lcd_check_next_stage(const void *blob, int wait); 144 145 /** 146 * Set up the maximum LCD size so we can size the frame buffer. 147 * 148 * @param blob fdt blob containing LCD information 149 */ 150 void tegra_lcd_early_init(const void *blob); 151 152 #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ 153