1 /* 2 * (C) Copyright 2010 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ASM_ARCH_TEGRA_DISPLAY_H 9 #define __ASM_ARCH_TEGRA_DISPLAY_H 10 11 #include <asm/arch/dc.h> 12 #include <fdtdec.h> 13 #include <asm/gpio.h> 14 15 /* This holds information about a window which can be displayed */ 16 struct disp_ctl_win { 17 enum win_color_depth_id fmt; /* Color depth/format */ 18 unsigned bpp; /* Bits per pixel */ 19 phys_addr_t phys_addr; /* Physical address in memory */ 20 unsigned x; /* Horizontal address offset (bytes) */ 21 unsigned y; /* Veritical address offset (bytes) */ 22 unsigned w; /* Width of source window */ 23 unsigned h; /* Height of source window */ 24 unsigned stride; /* Number of bytes per line */ 25 unsigned out_x; /* Left edge of output window (col) */ 26 unsigned out_y; /* Top edge of output window (row) */ 27 unsigned out_w; /* Width of output window in pixels */ 28 unsigned out_h; /* Height of output window in pixels */ 29 }; 30 31 #define FDT_LCD_TIMINGS 4 32 33 enum { 34 FDT_LCD_TIMING_REF_TO_SYNC, 35 FDT_LCD_TIMING_SYNC_WIDTH, 36 FDT_LCD_TIMING_BACK_PORCH, 37 FDT_LCD_TIMING_FRONT_PORCH, 38 39 FDT_LCD_TIMING_COUNT, 40 }; 41 42 enum lcd_cache_t { 43 FDT_LCD_CACHE_OFF = 0, 44 FDT_LCD_CACHE_WRITE_THROUGH = 1 << 0, 45 FDT_LCD_CACHE_WRITE_BACK = 1 << 1, 46 FDT_LCD_CACHE_FLUSH = 1 << 2, 47 FDT_LCD_CACHE_WRITE_BACK_FLUSH = FDT_LCD_CACHE_WRITE_BACK | 48 FDT_LCD_CACHE_FLUSH, 49 }; 50 51 /* Information about the display controller */ 52 struct fdt_disp_config { 53 int valid; /* config is valid */ 54 int width; /* width in pixels */ 55 int height; /* height in pixels */ 56 int bpp; /* number of bits per pixel */ 57 58 /* 59 * log2 of number of bpp, in general, unless it bpp is 24 in which 60 * case this field holds 24 also! This is a U-Boot thing. 61 */ 62 int log2_bpp; 63 struct disp_ctlr *disp; /* Display controller to use */ 64 fdt_addr_t frame_buffer; /* Address of frame buffer */ 65 unsigned pixel_clock; /* Pixel clock in Hz */ 66 uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ 67 uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ 68 int panel_node; /* node offset of panel information */ 69 }; 70 71 /* Information about the LCD panel */ 72 struct fdt_panel_config { 73 int pwm_channel; /* PWM channel to use for backlight */ 74 enum lcd_cache_t cache_type; 75 76 struct gpio_desc backlight_en; /* GPIO for backlight enable */ 77 struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ 78 struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ 79 struct gpio_desc panel_vdd; /* GPIO for panel vdd */ 80 /* 81 * Panel required timings 82 * Timing 1: delay between panel_vdd-rise and data-rise 83 * Timing 2: delay between data-rise and backlight_vdd-rise 84 * Timing 3: delay between backlight_vdd and pwm-rise 85 * Timing 4: delay between pwm-rise and backlight_en-rise 86 */ 87 uint panel_timings[FDT_LCD_TIMINGS]; 88 }; 89 90 /** 91 * Register a new display based on device tree configuration. 92 * 93 * The frame buffer can be positioned by U-Boot or overriden by the fdt. 94 * You should pass in the U-Boot address here, and check the contents of 95 * struct fdt_disp_config to see what was actually chosen. 96 * 97 * @param blob Device tree blob 98 * @param default_lcd_base Default address of LCD frame buffer 99 * @return 0 if ok, -1 on error (unsupported bits per pixel) 100 */ 101 int tegra_display_probe(const void *blob, void *default_lcd_base); 102 103 /** 104 * Return the current display configuration 105 * 106 * @return pointer to display configuration, or NULL if there is no valid 107 * config 108 */ 109 struct fdt_disp_config *tegra_display_get_config(void); 110 111 /** 112 * Perform the next stage of the LCD init if it is time to do so. 113 * 114 * LCD init can be time-consuming because of the number of delays we need 115 * while waiting for the backlight power supply, etc. This function can 116 * be called at various times during U-Boot operation to advance the 117 * initialization of the LCD to the next stage if sufficient time has 118 * passed since the last stage. It keeps track of what stage it is up to 119 * and the time that it is permitted to move to the next stage. 120 * 121 * The final call should have wait=1 to complete the init. 122 * 123 * @param blob fdt blob containing LCD information 124 * @param wait 1 to wait until all init is complete, and then return 125 * 0 to return immediately, potentially doing nothing if it is 126 * not yet time for the next init. 127 */ 128 int tegra_lcd_check_next_stage(const void *blob, int wait); 129 130 /** 131 * Set up the maximum LCD size so we can size the frame buffer. 132 * 133 * @param blob fdt blob containing LCD information 134 */ 135 void tegra_lcd_early_init(const void *blob); 136 137 #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ 138