1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 287540de3SWei Ni /* 387540de3SWei Ni * (C) Copyright 2010 487540de3SWei Ni * NVIDIA Corporation <www.nvidia.com> 587540de3SWei Ni */ 687540de3SWei Ni 787540de3SWei Ni #ifndef __ASM_ARCH_TEGRA_DISPLAY_H 887540de3SWei Ni #define __ASM_ARCH_TEGRA_DISPLAY_H 987540de3SWei Ni 102eb70de6SSimon Glass #include <asm/arch-tegra/dc.h> 1187540de3SWei Ni 1287540de3SWei Ni /* This holds information about a window which can be displayed */ 1387540de3SWei Ni struct disp_ctl_win { 1487540de3SWei Ni enum win_color_depth_id fmt; /* Color depth/format */ 1587540de3SWei Ni unsigned bpp; /* Bits per pixel */ 1687540de3SWei Ni phys_addr_t phys_addr; /* Physical address in memory */ 1787540de3SWei Ni unsigned x; /* Horizontal address offset (bytes) */ 1887540de3SWei Ni unsigned y; /* Veritical address offset (bytes) */ 1987540de3SWei Ni unsigned w; /* Width of source window */ 2087540de3SWei Ni unsigned h; /* Height of source window */ 2187540de3SWei Ni unsigned stride; /* Number of bytes per line */ 2287540de3SWei Ni unsigned out_x; /* Left edge of output window (col) */ 2387540de3SWei Ni unsigned out_y; /* Top edge of output window (row) */ 2487540de3SWei Ni unsigned out_w; /* Width of output window in pixels */ 2587540de3SWei Ni unsigned out_h; /* Height of output window in pixels */ 2687540de3SWei Ni }; 2787540de3SWei Ni 2887540de3SWei Ni #endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ 29