1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  * See file CREDITS for list of people who contributed to this
4  * project.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; either version 2 of
9  * the License, or (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19  * MA 02111-1307 USA
20  */
21 
22 /* Tegra2 clock control functions */
23 
24 #ifndef _CLOCK_H
25 #define _CLOCK_H
26 
27 /* Set of oscillator frequencies supported in the internal API. */
28 enum clock_osc_freq {
29 	/* All in MHz, so 13_0 is 13.0MHz */
30 	CLOCK_OSC_FREQ_13_0,
31 	CLOCK_OSC_FREQ_19_2,
32 	CLOCK_OSC_FREQ_12_0,
33 	CLOCK_OSC_FREQ_26_0,
34 
35 	CLOCK_OSC_FREQ_COUNT,
36 };
37 
38 /* The PLLs supported by the hardware */
39 enum clock_id {
40 	CLOCK_ID_FIRST,
41 	CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
42 	CLOCK_ID_MEMORY,
43 	CLOCK_ID_PERIPH,
44 	CLOCK_ID_AUDIO,
45 	CLOCK_ID_USB,
46 	CLOCK_ID_DISPLAY,
47 
48 	/* now the simple ones */
49 	CLOCK_ID_FIRST_SIMPLE,
50 	CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
51 	CLOCK_ID_EPCI,
52 	CLOCK_ID_SFROM32KHZ,
53 
54 	/* These are the base clocks (inputs to the Tegra SOC) */
55 	CLOCK_ID_32KHZ,
56 	CLOCK_ID_OSC,
57 
58 	CLOCK_ID_COUNT,	/* number of clocks */
59 	CLOCK_ID_NONE = -1,
60 };
61 
62 /* The clocks supported by the hardware */
63 enum periph_id {
64 	PERIPH_ID_FIRST,
65 
66 	/* Low word: 31:0 */
67 	PERIPH_ID_CPU = PERIPH_ID_FIRST,
68 	PERIPH_ID_RESERVED1,
69 	PERIPH_ID_RESERVED2,
70 	PERIPH_ID_AC97,
71 	PERIPH_ID_RTC,
72 	PERIPH_ID_TMR,
73 	PERIPH_ID_UART1,
74 	PERIPH_ID_UART2,
75 
76 	/* 8 */
77 	PERIPH_ID_GPIO,
78 	PERIPH_ID_SDMMC2,
79 	PERIPH_ID_SPDIF,
80 	PERIPH_ID_I2S1,
81 	PERIPH_ID_I2C1,
82 	PERIPH_ID_NDFLASH,
83 	PERIPH_ID_SDMMC1,
84 	PERIPH_ID_SDMMC4,
85 
86 	/* 16 */
87 	PERIPH_ID_TWC,
88 	PERIPH_ID_PWM,
89 	PERIPH_ID_I2S2,
90 	PERIPH_ID_EPP,
91 	PERIPH_ID_VI,
92 	PERIPH_ID_2D,
93 	PERIPH_ID_USBD,
94 	PERIPH_ID_ISP,
95 
96 	/* 24 */
97 	PERIPH_ID_3D,
98 	PERIPH_ID_IDE,
99 	PERIPH_ID_DISP2,
100 	PERIPH_ID_DISP1,
101 	PERIPH_ID_HOST1X,
102 	PERIPH_ID_VCP,
103 	PERIPH_ID_RESERVED30,
104 	PERIPH_ID_CACHE2,
105 
106 	/* Middle word: 63:32 */
107 	PERIPH_ID_MEM,
108 	PERIPH_ID_AHBDMA,
109 	PERIPH_ID_APBDMA,
110 	PERIPH_ID_RESERVED35,
111 	PERIPH_ID_KBC,
112 	PERIPH_ID_STAT_MON,
113 	PERIPH_ID_PMC,
114 	PERIPH_ID_FUSE,
115 
116 	/* 40 */
117 	PERIPH_ID_KFUSE,
118 	PERIPH_ID_SBC1,
119 	PERIPH_ID_SNOR,
120 	PERIPH_ID_SPI1,
121 	PERIPH_ID_SBC2,
122 	PERIPH_ID_XIO,
123 	PERIPH_ID_SBC3,
124 	PERIPH_ID_DVC_I2C,
125 
126 	/* 48 */
127 	PERIPH_ID_DSI,
128 	PERIPH_ID_TVO,
129 	PERIPH_ID_MIPI,
130 	PERIPH_ID_HDMI,
131 	PERIPH_ID_CSI,
132 	PERIPH_ID_TVDAC,
133 	PERIPH_ID_I2C2,
134 	PERIPH_ID_UART3,
135 
136 	/* 56 */
137 	PERIPH_ID_RESERVED56,
138 	PERIPH_ID_EMC,
139 	PERIPH_ID_USB2,
140 	PERIPH_ID_USB3,
141 	PERIPH_ID_MPE,
142 	PERIPH_ID_VDE,
143 	PERIPH_ID_BSEA,
144 	PERIPH_ID_BSEV,
145 
146 	/* Upper word 95:64 */
147 	PERIPH_ID_SPEEDO,
148 	PERIPH_ID_UART4,
149 	PERIPH_ID_UART5,
150 	PERIPH_ID_I2C3,
151 	PERIPH_ID_SBC4,
152 	PERIPH_ID_SDMMC3,
153 	PERIPH_ID_PCIE,
154 	PERIPH_ID_OWR,
155 
156 	/* 72 */
157 	PERIPH_ID_AFI,
158 	PERIPH_ID_CORESIGHT,
159 	PERIPH_ID_RESERVED74,
160 	PERIPH_ID_AVPUCQ,
161 	PERIPH_ID_RESERVED76,
162 	PERIPH_ID_RESERVED77,
163 	PERIPH_ID_RESERVED78,
164 	PERIPH_ID_RESERVED79,
165 
166 	/* 80 */
167 	PERIPH_ID_RESERVED80,
168 	PERIPH_ID_RESERVED81,
169 	PERIPH_ID_RESERVED82,
170 	PERIPH_ID_RESERVED83,
171 	PERIPH_ID_IRAMA,
172 	PERIPH_ID_IRAMB,
173 	PERIPH_ID_IRAMC,
174 	PERIPH_ID_IRAMD,
175 
176 	/* 88 */
177 	PERIPH_ID_CRAM2,
178 
179 	PERIPH_ID_COUNT,
180 	PERIPH_ID_NONE = -1,
181 };
182 
183 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
184 #define PERIPH_REG(id) ((id) >> 5)
185 
186 /* Mask value for a clock (within PERIPH_REG(id)) */
187 #define PERIPH_MASK(id) (1 << ((id) & 0x1f))
188 
189 /* return 1 if a PLL ID is in range, and not a simple PLL */
190 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
191 		(id) < CLOCK_ID_FIRST_SIMPLE)
192 
193 /* PLL stabilization delay in usec */
194 #define CLOCK_PLL_STABLE_DELAY_US 300
195 
196 /* return the current oscillator clock frequency */
197 enum clock_osc_freq clock_get_osc_freq(void);
198 
199 /**
200  * Start PLL using the provided configuration parameters.
201  *
202  * @param id	clock id
203  * @param divm	input divider
204  * @param divn	feedback divider
205  * @param divp	post divider 2^n
206  * @param cpcon	charge pump setup control
207  * @param lfcon	loop filter setup control
208  *
209  * @returns monotonic time in us that the PLL will be stable
210  */
211 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
212 		u32 divp, u32 cpcon, u32 lfcon);
213 
214 /**
215  * Read low-level parameters of a PLL.
216  *
217  * @param id	clock id to read (note: USB is not supported)
218  * @param divm	returns input divider
219  * @param divn	returns feedback divider
220  * @param divp	returns post divider 2^n
221  * @param cpcon	returns charge pump setup control
222  * @param lfcon	returns loop filter setup control
223  *
224  * @returns 0 if ok, -1 on error (invalid clock id)
225  */
226 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
227 		      u32 *divp, u32 *cpcon, u32 *lfcon);
228 
229 /*
230  * Enable a clock
231  *
232  * @param id	clock id
233  */
234 void clock_enable(enum periph_id clkid);
235 
236 /*
237  * Disable a clock
238  *
239  * @param id	clock id
240  */
241 void clock_disable(enum periph_id clkid);
242 
243 /*
244  * Set whether a clock is enabled or disabled.
245  *
246  * @param id		clock id
247  * @param enable	1 to enable, 0 to disable
248  */
249 void clock_set_enable(enum periph_id clkid, int enable);
250 
251 /**
252  * Reset a peripheral. This puts it in reset, waits for a delay, then takes
253  * it out of reset and waits for th delay again.
254  *
255  * @param periph_id	peripheral to reset
256  * @param us_delay	time to delay in microseconds
257  */
258 void reset_periph(enum periph_id periph_id, int us_delay);
259 
260 /**
261  * Put a peripheral into or out of reset.
262  *
263  * @param periph_id	peripheral to reset
264  * @param enable	1 to put into reset, 0 to take out of reset
265  */
266 void reset_set_enable(enum periph_id periph_id, int enable);
267 
268 
269 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
270 enum crc_reset_id {
271 	/* Things we can hold in reset for each CPU */
272 	crc_rst_cpu = 1,
273 	crc_rst_de = 1 << 2,	/* What is de? */
274 	crc_rst_watchdog = 1 << 3,
275 	crc_rst_debug = 1 << 4,
276 };
277 
278 /**
279  * Put parts of the CPU complex into or out of reset.\
280  *
281  * @param cpu		cpu number (0 or 1 on Tegra2)
282  * @param which		which parts of the complex to affect (OR of crc_reset_id)
283  * @param reset		1 to assert reset, 0 to de-assert
284  */
285 void reset_cmplx_set_enable(int cpu, int which, int reset);
286 
287 /**
288  * Set the source for a peripheral clock. This plus the divisor sets the
289  * clock rate. You need to look up the datasheet to see the meaning of the
290  * source parameter as it changes for each peripheral.
291  *
292  * Warning: This function is only for use pre-relocation. Please use
293  * clock_start_periph_pll() instead.
294  *
295  * @param periph_id	peripheral to adjust
296  * @param source	source clock (0, 1, 2 or 3)
297  */
298 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
299 
300 /**
301  * Set the source and divisor for a peripheral clock. This sets the
302  * clock rate. You need to look up the datasheet to see the meaning of the
303  * source parameter as it changes for each peripheral.
304  *
305  * Warning: This function is only for use pre-relocation. Please use
306  * clock_start_periph_pll() instead.
307  *
308  * @param periph_id	peripheral to adjust
309  * @param source	source clock (0, 1, 2 or 3)
310  * @param divisor	divisor value to use
311  */
312 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
313 		unsigned divisor);
314 
315 /**
316  * Start a peripheral PLL clock at the given rate. This also resets the
317  * peripheral.
318  *
319  * @param periph_id	peripheral to start
320  * @param parent	PLL id of required parent clock
321  * @param rate		Required clock rate in Hz
322  * @return rate selected in Hz, or -1U if something went wrong
323  */
324 unsigned clock_start_periph_pll(enum periph_id periph_id,
325 		enum clock_id parent, unsigned rate);
326 
327 /**
328  * Returns the rate of a peripheral clock in Hz. Since the caller almost
329  * certainly knows the parent clock (having just set it) we require that
330  * this be passed in so we don't need to work it out.
331  *
332  * @param periph_id	peripheral to start
333  * @param parent	PLL id of parent clock (used to calculate rate, you
334  *			must know this!)
335  * @return clock rate of peripheral in Hz
336  */
337 unsigned long clock_get_periph_rate(enum periph_id periph_id,
338 		enum clock_id parent);
339 
340 /**
341  * Adjust peripheral PLL clock to the given rate. This does not reset the
342  * peripheral. If a second stage divisor is not available, pass NULL for
343  * extra_div. If it is available, then this parameter will return the
344  * divisor selected (which will be a power of 2 from 1 to 256).
345  *
346  * @param periph_id	peripheral to start
347  * @param parent	PLL id of required parent clock
348  * @param rate		Required clock rate in Hz
349  * @param extra_div	value for the second-stage divisor (NULL if one is
350 			not available)
351  * @return rate selected in Hz, or -1U if something went wrong
352  */
353 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
354 		enum clock_id parent, unsigned rate, int *extra_div);
355 
356 /**
357  * Returns the clock rate of a specified clock, in Hz.
358  *
359  * @param parent	PLL id of clock to check
360  * @return rate of clock in Hz
361  */
362 unsigned clock_get_rate(enum clock_id clkid);
363 
364 /**
365  * Start up a UART using low-level calls
366  *
367  * Prior to relocation clock_start_periph_pll() cannot be called. This
368  * function provides a way to set up a UART using low-level calls which
369  * do not require BSS.
370  *
371  * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
372  */
373 void clock_ll_start_uart(enum periph_id periph_id);
374 
375 /**
376  * Decode a peripheral ID from a device tree node.
377  *
378  * This works by looking up the peripheral's 'clocks' node and reading out
379  * the second cell, which is the clock number / peripheral ID.
380  *
381  * @param blob		FDT blob to use
382  * @param node		Node to look at
383  * @return peripheral ID, or PERIPH_ID_NONE if none
384  */
385 enum periph_id clock_decode_periph_id(const void *blob, int node);
386 
387 /**
388  * Checks if the oscillator bypass is enabled (XOBP bit)
389  *
390  * @return 1 if bypass is enabled, 0 if not
391  */
392 int clock_get_osc_bypass(void);
393 
394 /*
395  * Checks that clocks are valid and prints a warning if not
396  *
397  * @return 0 if ok, -1 on error
398  */
399 int clock_verify(void);
400 
401 /* Initialize the clocks */
402 void clock_init(void);
403 
404 /* Initialize the PLLs */
405 void clock_early_init(void);
406 
407 #endif
408