1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra20 clock PLL tables */ 9 10 #ifndef _CLOCK_TABLES_H_ 11 #define _CLOCK_TABLES_H_ 12 13 /* The PLLs supported by the hardware */ 14 enum clock_id { 15 CLOCK_ID_FIRST, 16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST, 17 CLOCK_ID_MEMORY, 18 CLOCK_ID_PERIPH, 19 CLOCK_ID_AUDIO, 20 CLOCK_ID_USB, 21 CLOCK_ID_DISPLAY, 22 23 /* now the simple ones */ 24 CLOCK_ID_FIRST_SIMPLE, 25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE, 26 CLOCK_ID_EPCI, 27 CLOCK_ID_SFROM32KHZ, 28 29 /* These are the base clocks (inputs to the Tegra SOC) */ 30 CLOCK_ID_32KHZ, 31 CLOCK_ID_OSC, 32 CLOCK_ID_CLK_M, 33 34 CLOCK_ID_COUNT, /* number of clocks */ 35 CLOCK_ID_NONE = -1, 36 }; 37 38 /* The clocks supported by the hardware */ 39 enum periph_id { 40 PERIPH_ID_FIRST, 41 42 /* Low word: 31:0 */ 43 PERIPH_ID_CPU = PERIPH_ID_FIRST, 44 PERIPH_ID_RESERVED1, 45 PERIPH_ID_RESERVED2, 46 PERIPH_ID_AC97, 47 PERIPH_ID_RTC, 48 PERIPH_ID_TMR, 49 PERIPH_ID_UART1, 50 PERIPH_ID_UART2, 51 52 /* 8 */ 53 PERIPH_ID_GPIO, 54 PERIPH_ID_SDMMC2, 55 PERIPH_ID_SPDIF, 56 PERIPH_ID_I2S1, 57 PERIPH_ID_I2C1, 58 PERIPH_ID_NDFLASH, 59 PERIPH_ID_SDMMC1, 60 PERIPH_ID_SDMMC4, 61 62 /* 16 */ 63 PERIPH_ID_TWC, 64 PERIPH_ID_PWM, 65 PERIPH_ID_I2S2, 66 PERIPH_ID_EPP, 67 PERIPH_ID_VI, 68 PERIPH_ID_2D, 69 PERIPH_ID_USBD, 70 PERIPH_ID_ISP, 71 72 /* 24 */ 73 PERIPH_ID_3D, 74 PERIPH_ID_IDE, 75 PERIPH_ID_DISP2, 76 PERIPH_ID_DISP1, 77 PERIPH_ID_HOST1X, 78 PERIPH_ID_VCP, 79 PERIPH_ID_RESERVED30, 80 PERIPH_ID_CACHE2, 81 82 /* Middle word: 63:32 */ 83 PERIPH_ID_MEM, 84 PERIPH_ID_AHBDMA, 85 PERIPH_ID_APBDMA, 86 PERIPH_ID_RESERVED35, 87 PERIPH_ID_KBC, 88 PERIPH_ID_STAT_MON, 89 PERIPH_ID_PMC, 90 PERIPH_ID_FUSE, 91 92 /* 40 */ 93 PERIPH_ID_KFUSE, 94 PERIPH_ID_SBC1, 95 PERIPH_ID_SNOR, 96 PERIPH_ID_SPI1, 97 PERIPH_ID_SBC2, 98 PERIPH_ID_XIO, 99 PERIPH_ID_SBC3, 100 PERIPH_ID_DVC_I2C, 101 102 /* 48 */ 103 PERIPH_ID_DSI, 104 PERIPH_ID_TVO, 105 PERIPH_ID_MIPI, 106 PERIPH_ID_HDMI, 107 PERIPH_ID_CSI, 108 PERIPH_ID_TVDAC, 109 PERIPH_ID_I2C2, 110 PERIPH_ID_UART3, 111 112 /* 56 */ 113 PERIPH_ID_RESERVED56, 114 PERIPH_ID_EMC, 115 PERIPH_ID_USB2, 116 PERIPH_ID_USB3, 117 PERIPH_ID_MPE, 118 PERIPH_ID_VDE, 119 PERIPH_ID_BSEA, 120 PERIPH_ID_BSEV, 121 122 /* Upper word 95:64 */ 123 PERIPH_ID_SPEEDO, 124 PERIPH_ID_UART4, 125 PERIPH_ID_UART5, 126 PERIPH_ID_I2C3, 127 PERIPH_ID_SBC4, 128 PERIPH_ID_SDMMC3, 129 PERIPH_ID_PCIE, 130 PERIPH_ID_OWR, 131 132 /* 72 */ 133 PERIPH_ID_AFI, 134 PERIPH_ID_CORESIGHT, 135 PERIPH_ID_PCIEXCLK, 136 PERIPH_ID_AVPUCQ, 137 PERIPH_ID_RESERVED76, 138 PERIPH_ID_RESERVED77, 139 PERIPH_ID_RESERVED78, 140 PERIPH_ID_RESERVED79, 141 142 /* 80 */ 143 PERIPH_ID_RESERVED80, 144 PERIPH_ID_RESERVED81, 145 PERIPH_ID_RESERVED82, 146 PERIPH_ID_RESERVED83, 147 PERIPH_ID_IRAMA, 148 PERIPH_ID_IRAMB, 149 PERIPH_ID_IRAMC, 150 PERIPH_ID_IRAMD, 151 152 /* 88 */ 153 PERIPH_ID_CRAM2, 154 PERIPH_ID_SYNC_CLK_DOUBLER, 155 PERIPH_ID_CLK_M_DOUBLER, 156 PERIPH_ID_RESERVED91, 157 PERIPH_ID_SUS_OUT, 158 PERIPH_ID_DEV2_OUT, 159 PERIPH_ID_DEV1_OUT, 160 161 PERIPH_ID_COUNT, 162 PERIPH_ID_NONE = -1, 163 }; 164 165 enum pll_out_id { 166 PLL_OUT1, 167 PLL_OUT2, 168 PLL_OUT3, 169 PLL_OUT4 170 }; 171 172 /* Converts a clock number to a clock register: 0=L, 1=H, 2=U */ 173 #define PERIPH_REG(id) ((id) >> 5) 174 175 /* Mask value for a clock (within PERIPH_REG(id)) */ 176 #define PERIPH_MASK(id) (1 << ((id) & 0x1f)) 177 178 /* return 1 if a PLL ID is in range, and not a simple PLL */ 179 #define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \ 180 (id) < CLOCK_ID_FIRST_SIMPLE) 181 182 /* return 1 if a peripheral ID is in range */ 183 #define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \ 184 (id) < PERIPH_ID_COUNT) 185 186 #endif /* _CLOCK_TABLES_H_ */ 187