1 /*
2  * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: GPL-2.0+
5  */
6 
7 #ifndef _TEGRA124_PINMUX_H_
8 #define _TEGRA124_PINMUX_H_
9 
10 enum pmux_pingrp {
11 	PMUX_PINGRP_ULPI_DATA0_PO1,
12 	PMUX_PINGRP_ULPI_DATA1_PO2,
13 	PMUX_PINGRP_ULPI_DATA2_PO3,
14 	PMUX_PINGRP_ULPI_DATA3_PO4,
15 	PMUX_PINGRP_ULPI_DATA4_PO5,
16 	PMUX_PINGRP_ULPI_DATA5_PO6,
17 	PMUX_PINGRP_ULPI_DATA6_PO7,
18 	PMUX_PINGRP_ULPI_DATA7_PO0,
19 	PMUX_PINGRP_ULPI_CLK_PY0,
20 	PMUX_PINGRP_ULPI_DIR_PY1,
21 	PMUX_PINGRP_ULPI_NXT_PY2,
22 	PMUX_PINGRP_ULPI_STP_PY3,
23 	PMUX_PINGRP_DAP3_FS_PP0,
24 	PMUX_PINGRP_DAP3_DIN_PP1,
25 	PMUX_PINGRP_DAP3_DOUT_PP2,
26 	PMUX_PINGRP_DAP3_SCLK_PP3,
27 	PMUX_PINGRP_PV0,
28 	PMUX_PINGRP_PV1,
29 	PMUX_PINGRP_SDMMC1_CLK_PZ0,
30 	PMUX_PINGRP_SDMMC1_CMD_PZ1,
31 	PMUX_PINGRP_SDMMC1_DAT3_PY4,
32 	PMUX_PINGRP_SDMMC1_DAT2_PY5,
33 	PMUX_PINGRP_SDMMC1_DAT1_PY6,
34 	PMUX_PINGRP_SDMMC1_DAT0_PY7,
35 	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
36 	PMUX_PINGRP_CLK2_REQ_PCC5,
37 	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
38 	PMUX_PINGRP_DDC_SCL_PV4,
39 	PMUX_PINGRP_DDC_SDA_PV5,
40 	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
41 	PMUX_PINGRP_UART2_TXD_PC2,
42 	PMUX_PINGRP_UART2_RTS_N_PJ6,
43 	PMUX_PINGRP_UART2_CTS_N_PJ5,
44 	PMUX_PINGRP_UART3_TXD_PW6,
45 	PMUX_PINGRP_UART3_RXD_PW7,
46 	PMUX_PINGRP_UART3_CTS_N_PA1,
47 	PMUX_PINGRP_UART3_RTS_N_PC0,
48 	PMUX_PINGRP_PU0,
49 	PMUX_PINGRP_PU1,
50 	PMUX_PINGRP_PU2,
51 	PMUX_PINGRP_PU3,
52 	PMUX_PINGRP_PU4,
53 	PMUX_PINGRP_PU5,
54 	PMUX_PINGRP_PU6,
55 	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
56 	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
57 	PMUX_PINGRP_DAP4_FS_PP4,
58 	PMUX_PINGRP_DAP4_DIN_PP5,
59 	PMUX_PINGRP_DAP4_DOUT_PP6,
60 	PMUX_PINGRP_DAP4_SCLK_PP7,
61 	PMUX_PINGRP_CLK3_OUT_PEE0,
62 	PMUX_PINGRP_CLK3_REQ_PEE1,
63 	PMUX_PINGRP_PC7,
64 	PMUX_PINGRP_PI5,
65 	PMUX_PINGRP_PI7,
66 	PMUX_PINGRP_PK0,
67 	PMUX_PINGRP_PK1,
68 	PMUX_PINGRP_PJ0,
69 	PMUX_PINGRP_PJ2,
70 	PMUX_PINGRP_PK3,
71 	PMUX_PINGRP_PK4,
72 	PMUX_PINGRP_PK2,
73 	PMUX_PINGRP_PI3,
74 	PMUX_PINGRP_PI6,
75 	PMUX_PINGRP_PG0,
76 	PMUX_PINGRP_PG1,
77 	PMUX_PINGRP_PG2,
78 	PMUX_PINGRP_PG3,
79 	PMUX_PINGRP_PG4,
80 	PMUX_PINGRP_PG5,
81 	PMUX_PINGRP_PG6,
82 	PMUX_PINGRP_PG7,
83 	PMUX_PINGRP_PH0,
84 	PMUX_PINGRP_PH1,
85 	PMUX_PINGRP_PH2,
86 	PMUX_PINGRP_PH3,
87 	PMUX_PINGRP_PH4,
88 	PMUX_PINGRP_PH5,
89 	PMUX_PINGRP_PH6,
90 	PMUX_PINGRP_PH7,
91 	PMUX_PINGRP_PJ7,
92 	PMUX_PINGRP_PB0,
93 	PMUX_PINGRP_PB1,
94 	PMUX_PINGRP_PK7,
95 	PMUX_PINGRP_PI0,
96 	PMUX_PINGRP_PI1,
97 	PMUX_PINGRP_PI2,
98 	PMUX_PINGRP_PI4,
99 	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
100 	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
101 	PMUX_PINGRP_SDMMC4_CLK_PCC4,
102 	PMUX_PINGRP_SDMMC4_CMD_PT7,
103 	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
104 	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
105 	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
106 	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
107 	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
108 	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
109 	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
110 	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
111 	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
112 	PMUX_PINGRP_PCC1,
113 	PMUX_PINGRP_PBB0,
114 	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
115 	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
116 	PMUX_PINGRP_PBB3,
117 	PMUX_PINGRP_PBB4,
118 	PMUX_PINGRP_PBB5,
119 	PMUX_PINGRP_PBB6,
120 	PMUX_PINGRP_PBB7,
121 	PMUX_PINGRP_PCC2,
122 	PMUX_PINGRP_JTAG_RTCK,
123 	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
124 	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
125 	PMUX_PINGRP_KB_ROW0_PR0,
126 	PMUX_PINGRP_KB_ROW1_PR1,
127 	PMUX_PINGRP_KB_ROW2_PR2,
128 	PMUX_PINGRP_KB_ROW3_PR3,
129 	PMUX_PINGRP_KB_ROW4_PR4,
130 	PMUX_PINGRP_KB_ROW5_PR5,
131 	PMUX_PINGRP_KB_ROW6_PR6,
132 	PMUX_PINGRP_KB_ROW7_PR7,
133 	PMUX_PINGRP_KB_ROW8_PS0,
134 	PMUX_PINGRP_KB_ROW9_PS1,
135 	PMUX_PINGRP_KB_ROW10_PS2,
136 	PMUX_PINGRP_KB_ROW11_PS3,
137 	PMUX_PINGRP_KB_ROW12_PS4,
138 	PMUX_PINGRP_KB_ROW13_PS5,
139 	PMUX_PINGRP_KB_ROW14_PS6,
140 	PMUX_PINGRP_KB_ROW15_PS7,
141 	PMUX_PINGRP_KB_COL0_PQ0,
142 	PMUX_PINGRP_KB_COL1_PQ1,
143 	PMUX_PINGRP_KB_COL2_PQ2,
144 	PMUX_PINGRP_KB_COL3_PQ3,
145 	PMUX_PINGRP_KB_COL4_PQ4,
146 	PMUX_PINGRP_KB_COL5_PQ5,
147 	PMUX_PINGRP_KB_COL6_PQ6,
148 	PMUX_PINGRP_KB_COL7_PQ7,
149 	PMUX_PINGRP_CLK_32K_OUT_PA0,
150 	PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
151 	PMUX_PINGRP_CPU_PWR_REQ,
152 	PMUX_PINGRP_PWR_INT_N,
153 	PMUX_PINGRP_CLK_32K_IN,
154 	PMUX_PINGRP_OWR,
155 	PMUX_PINGRP_DAP1_FS_PN0,
156 	PMUX_PINGRP_DAP1_DIN_PN1,
157 	PMUX_PINGRP_DAP1_DOUT_PN2,
158 	PMUX_PINGRP_DAP1_SCLK_PN3,
159 	PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
160 	PMUX_PINGRP_DAP_MCLK1_PW4,
161 	PMUX_PINGRP_SPDIF_IN_PK6,
162 	PMUX_PINGRP_SPDIF_OUT_PK5,
163 	PMUX_PINGRP_DAP2_FS_PA2,
164 	PMUX_PINGRP_DAP2_DIN_PA4,
165 	PMUX_PINGRP_DAP2_DOUT_PA5,
166 	PMUX_PINGRP_DAP2_SCLK_PA3,
167 	PMUX_PINGRP_DVFS_PWM_PX0,
168 	PMUX_PINGRP_GPIO_X1_AUD_PX1,
169 	PMUX_PINGRP_GPIO_X3_AUD_PX3,
170 	PMUX_PINGRP_DVFS_CLK_PX2,
171 	PMUX_PINGRP_GPIO_X4_AUD_PX4,
172 	PMUX_PINGRP_GPIO_X5_AUD_PX5,
173 	PMUX_PINGRP_GPIO_X6_AUD_PX6,
174 	PMUX_PINGRP_GPIO_X7_AUD_PX7,
175 	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
176 	PMUX_PINGRP_SDMMC3_CMD_PA7,
177 	PMUX_PINGRP_SDMMC3_DAT0_PB7,
178 	PMUX_PINGRP_SDMMC3_DAT1_PB6,
179 	PMUX_PINGRP_SDMMC3_DAT2_PB5,
180 	PMUX_PINGRP_SDMMC3_DAT3_PB4,
181 	PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
182 	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
183 	PMUX_PINGRP_PEX_WAKE_N_PDD3,
184 	PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
185 	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
186 	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
187 	PMUX_PINGRP_SDMMC1_WP_N_PV3,
188 	PMUX_PINGRP_SDMMC3_CD_N_PV2,
189 	PMUX_PINGRP_GPIO_W2_AUD_PW2,
190 	PMUX_PINGRP_GPIO_W3_AUD_PW3,
191 	PMUX_PINGRP_USB_VBUS_EN0_PN4,
192 	PMUX_PINGRP_USB_VBUS_EN1_PN5,
193 	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
194 	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
195 	PMUX_PINGRP_GMI_CLK_LB,
196 	PMUX_PINGRP_RESET_OUT_N,
197 	PMUX_PINGRP_KB_ROW16_PT0,
198 	PMUX_PINGRP_KB_ROW17_PT1,
199 	PMUX_PINGRP_USB_VBUS_EN2_PFF1,
200 	PMUX_PINGRP_PFF2,
201 	PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
202 	PMUX_PINGRP_COUNT,
203 };
204 
205 enum pmux_drvgrp {
206 	PMUX_DRVGRP_AO1,
207 	PMUX_DRVGRP_AO2,
208 	PMUX_DRVGRP_AT1,
209 	PMUX_DRVGRP_AT2,
210 	PMUX_DRVGRP_AT3,
211 	PMUX_DRVGRP_AT4,
212 	PMUX_DRVGRP_AT5,
213 	PMUX_DRVGRP_CDEV1,
214 	PMUX_DRVGRP_CDEV2,
215 	PMUX_DRVGRP_DAP1 = (0x28 / 4),
216 	PMUX_DRVGRP_DAP2,
217 	PMUX_DRVGRP_DAP3,
218 	PMUX_DRVGRP_DAP4,
219 	PMUX_DRVGRP_DBG,
220 	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
221 	PMUX_DRVGRP_SPI,
222 	PMUX_DRVGRP_UAA,
223 	PMUX_DRVGRP_UAB,
224 	PMUX_DRVGRP_UART2,
225 	PMUX_DRVGRP_UART3,
226 	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
227 	PMUX_DRVGRP_DDC = (0x94 / 4),
228 	PMUX_DRVGRP_GMA,
229 	PMUX_DRVGRP_GME = (0xa8 / 4),
230 	PMUX_DRVGRP_GMF,
231 	PMUX_DRVGRP_GMG,
232 	PMUX_DRVGRP_GMH,
233 	PMUX_DRVGRP_OWR,
234 	PMUX_DRVGRP_UDA,
235 	PMUX_DRVGRP_GPV,
236 	PMUX_DRVGRP_DEV3,
237 	PMUX_DRVGRP_CEC = (0xd0 / 4),
238 	PMUX_DRVGRP_AT6 = (0x12c / 4),
239 	PMUX_DRVGRP_DAP5,
240 	PMUX_DRVGRP_USB_VBUS_EN,
241 	PMUX_DRVGRP_AO3 = (0x140 / 4),
242 	PMUX_DRVGRP_AO0 = (0x148 / 4),
243 	PMUX_DRVGRP_HV0,
244 	PMUX_DRVGRP_SDIO4 = (0x15c / 4),
245 	PMUX_DRVGRP_AO4,
246 	PMUX_DRVGRP_COUNT,
247 };
248 
249 enum pmux_func {
250 	PMUX_FUNC_DEFAULT,
251 	PMUX_FUNC_BLINK,
252 	PMUX_FUNC_CCLA,
253 	PMUX_FUNC_CEC,
254 	PMUX_FUNC_CLDVFS,
255 	PMUX_FUNC_CLK,
256 	PMUX_FUNC_CLK12,
257 	PMUX_FUNC_CPU,
258 	PMUX_FUNC_DAP,
259 	PMUX_FUNC_DAP1,
260 	PMUX_FUNC_DAP2,
261 	PMUX_FUNC_DEV3,
262 	PMUX_FUNC_DISPLAYA,
263 	PMUX_FUNC_DISPLAYA_ALT,
264 	PMUX_FUNC_DISPLAYB,
265 	PMUX_FUNC_DP,
266 	PMUX_FUNC_DTV,
267 	PMUX_FUNC_EXTPERIPH1,
268 	PMUX_FUNC_EXTPERIPH2,
269 	PMUX_FUNC_EXTPERIPH3,
270 	PMUX_FUNC_GMI,
271 	PMUX_FUNC_GMI_ALT,
272 	PMUX_FUNC_HDA,
273 	PMUX_FUNC_HSI,
274 	PMUX_FUNC_I2C1,
275 	PMUX_FUNC_I2C2,
276 	PMUX_FUNC_I2C3,
277 	PMUX_FUNC_I2C4,
278 	PMUX_FUNC_I2CPWR,
279 	PMUX_FUNC_I2S0,
280 	PMUX_FUNC_I2S1,
281 	PMUX_FUNC_I2S2,
282 	PMUX_FUNC_I2S3,
283 	PMUX_FUNC_I2S4,
284 	PMUX_FUNC_IRDA,
285 	PMUX_FUNC_KBC,
286 	PMUX_FUNC_OWR,
287 	PMUX_FUNC_PE,
288 	PMUX_FUNC_PE0,
289 	PMUX_FUNC_PE1,
290 	PMUX_FUNC_PMI,
291 	PMUX_FUNC_PWM0,
292 	PMUX_FUNC_PWM1,
293 	PMUX_FUNC_PWM2,
294 	PMUX_FUNC_PWM3,
295 	PMUX_FUNC_PWRON,
296 	PMUX_FUNC_RESET_OUT_N,
297 	PMUX_FUNC_RTCK,
298 	PMUX_FUNC_SATA,
299 	PMUX_FUNC_SDMMC1,
300 	PMUX_FUNC_SDMMC2,
301 	PMUX_FUNC_SDMMC3,
302 	PMUX_FUNC_SDMMC4,
303 	PMUX_FUNC_SOC,
304 	PMUX_FUNC_SPDIF,
305 	PMUX_FUNC_SPI1,
306 	PMUX_FUNC_SPI2,
307 	PMUX_FUNC_SPI3,
308 	PMUX_FUNC_SPI4,
309 	PMUX_FUNC_SPI5,
310 	PMUX_FUNC_SPI6,
311 	PMUX_FUNC_SYS,
312 	PMUX_FUNC_TMDS,
313 	PMUX_FUNC_TRACE,
314 	PMUX_FUNC_UARTA,
315 	PMUX_FUNC_UARTB,
316 	PMUX_FUNC_UARTC,
317 	PMUX_FUNC_UARTD,
318 	PMUX_FUNC_ULPI,
319 	PMUX_FUNC_USB,
320 	PMUX_FUNC_VGP1,
321 	PMUX_FUNC_VGP2,
322 	PMUX_FUNC_VGP3,
323 	PMUX_FUNC_VGP4,
324 	PMUX_FUNC_VGP5,
325 	PMUX_FUNC_VGP6,
326 	PMUX_FUNC_VI,
327 	PMUX_FUNC_VI_ALT1,
328 	PMUX_FUNC_VI_ALT3,
329 	PMUX_FUNC_VIMCLK2,
330 	PMUX_FUNC_VIMCLK2_ALT,
331 	PMUX_FUNC_RSVD1,
332 	PMUX_FUNC_RSVD2,
333 	PMUX_FUNC_RSVD3,
334 	PMUX_FUNC_RSVD4,
335 	PMUX_FUNC_COUNT,
336 };
337 
338 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
339 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
340 #define TEGRA_PMX_SOC_HAS_DRVGRPS
341 #define TEGRA_PMX_GRPS_HAVE_LPMD
342 #define TEGRA_PMX_GRPS_HAVE_SCHMT
343 #define TEGRA_PMX_GRPS_HAVE_HSM
344 #define TEGRA_PMX_PINS_HAVE_E_INPUT
345 #define TEGRA_PMX_PINS_HAVE_LOCK
346 #define TEGRA_PMX_PINS_HAVE_OD
347 #define TEGRA_PMX_PINS_HAVE_IO_RESET
348 #define TEGRA_PMX_PINS_HAVE_RCV_SEL
349 #include <asm/arch-tegra/pinmux.h>
350 
351 #endif /* _TEGRA124_PINMUX_H_ */
352