1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _TEGRA124_MC_H_ 18 #define _TEGRA124_MC_H_ 19 20 /** 21 * Defines the memory controller registers we need/care about 22 */ 23 struct mc_ctlr { 24 u32 reserved0[4]; /* offset 0x00 - 0x0C */ 25 u32 mc_smmu_config; /* offset 0x10 */ 26 u32 mc_smmu_tlb_config; /* offset 0x14 */ 27 u32 mc_smmu_ptc_config; /* offset 0x18 */ 28 u32 mc_smmu_ptb_asid; /* offset 0x1C */ 29 u32 mc_smmu_ptb_data; /* offset 0x20 */ 30 u32 reserved1[3]; /* offset 0x24 - 0x2C */ 31 u32 mc_smmu_tlb_flush; /* offset 0x30 */ 32 u32 mc_smmu_ptc_flush; /* offset 0x34 */ 33 u32 reserved2[6]; /* offset 0x38 - 0x4C */ 34 u32 mc_emem_cfg; /* offset 0x50 */ 35 u32 mc_emem_adr_cfg; /* offset 0x54 */ 36 u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 37 u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 38 u32 reserved3[12]; /* offset 0x60 - 0x8C */ 39 u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 40 u32 reserved4[338]; /* offset 0x100 - 0x644 */ 41 u32 mc_video_protect_bom; /* offset 0x648 */ 42 u32 mc_video_protect_size_mb; /* offset 0x64c */ 43 u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 44 }; 45 46 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) 47 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) 48 49 #endif /* _TEGRA124_MC_H_ */ 50