1 /* 2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _TEGRA124_MC_H_ 18 #define _TEGRA124_MC_H_ 19 20 /** 21 * Defines the memory controller registers we need/care about 22 */ 23 struct mc_ctlr { 24 u32 reserved0[4]; /* offset 0x00 - 0x0C */ 25 u32 mc_smmu_config; /* offset 0x10 */ 26 u32 mc_smmu_tlb_config; /* offset 0x14 */ 27 u32 mc_smmu_ptc_config; /* offset 0x18 */ 28 u32 mc_smmu_ptb_asid; /* offset 0x1C */ 29 u32 mc_smmu_ptb_data; /* offset 0x20 */ 30 u32 reserved1[3]; /* offset 0x24 - 0x2C */ 31 u32 mc_smmu_tlb_flush; /* offset 0x30 */ 32 u32 mc_smmu_ptc_flush; /* offset 0x34 */ 33 u32 reserved2[6]; /* offset 0x38 - 0x4C */ 34 u32 mc_emem_cfg; /* offset 0x50 */ 35 u32 mc_emem_adr_cfg; /* offset 0x54 */ 36 u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ 37 u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ 38 u32 reserved3[4]; /* offset 0x60 - 0x6C */ 39 u32 mc_security_cfg0; /* offset 0x70 */ 40 u32 mc_security_cfg1; /* offset 0x74 */ 41 u32 reserved4[6]; /* offset 0x7C - 0x8C */ 42 u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ 43 u32 reserved5[74]; /* offset 0x100 - 0x224 */ 44 u32 mc_smmu_translation_enable_0; /* offset 0x228 */ 45 u32 mc_smmu_translation_enable_1; /* offset 0x22C */ 46 u32 mc_smmu_translation_enable_2; /* offset 0x230 */ 47 u32 mc_smmu_translation_enable_3; /* offset 0x234 */ 48 u32 mc_smmu_afi_asid; /* offset 0x238 */ 49 u32 mc_smmu_avpc_asid; /* offset 0x23C */ 50 u32 mc_smmu_dc_asid; /* offset 0x240 */ 51 u32 mc_smmu_dcb_asid; /* offset 0x244 */ 52 u32 reserved6[2]; /* offset 0x248 - 0x24C */ 53 u32 mc_smmu_hc_asid; /* offset 0x250 */ 54 u32 mc_smmu_hda_asid; /* offset 0x254 */ 55 u32 mc_smmu_isp2_asid; /* offset 0x258 */ 56 u32 reserved7[2]; /* offset 0x25C - 0x260 */ 57 u32 mc_smmu_msenc_asid; /* offset 0x264 */ 58 u32 mc_smmu_nv_asid; /* offset 0x268 */ 59 u32 mc_smmu_nv2_asid; /* offset 0x26C */ 60 u32 mc_smmu_ppcs_asid; /* offset 0x270 */ 61 u32 mc_smmu_sata_asid; /* offset 0x274 */ 62 u32 reserved8[1]; /* offset 0x278 */ 63 u32 mc_smmu_vde_asid; /* offset 0x27C */ 64 u32 mc_smmu_vi_asid; /* offset 0x280 */ 65 u32 mc_smmu_vic_asid; /* offset 0x284 */ 66 u32 mc_smmu_xusb_host_asid; /* offset 0x288 */ 67 u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */ 68 u32 reserved9[1]; /* offset 0x290 */ 69 u32 mc_smmu_tsec_asid; /* offset 0x294 */ 70 u32 mc_smmu_ppcs1_asid; /* offset 0x298 */ 71 u32 reserved10[235]; /* offset 0x29C - 0x644 */ 72 u32 mc_video_protect_bom; /* offset 0x648 */ 73 u32 mc_video_protect_size_mb; /* offset 0x64c */ 74 u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ 75 }; 76 77 #define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0) 78 79 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0) 80 #define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0) 81 82 #endif /* _TEGRA124_MC_H_ */ 83