1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2999c6bafSTom Warren /* 3999c6bafSTom Warren * (C) Copyright 2013 4999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 5999c6bafSTom Warren */ 6999c6bafSTom Warren 7999c6bafSTom Warren /* Tegra124 high-level function multiplexing */ 8999c6bafSTom Warren 9999c6bafSTom Warren #ifndef _TEGRA124_FUNCMUX_H_ 10999c6bafSTom Warren #define _TEGRA124_FUNCMUX_H_ 11999c6bafSTom Warren 12999c6bafSTom Warren #include <asm/arch-tegra/funcmux.h> 13999c6bafSTom Warren 14999c6bafSTom Warren /* Configs supported by the func mux */ 15999c6bafSTom Warren enum { 16999c6bafSTom Warren FUNCMUX_DEFAULT = 0, /* default config */ 17999c6bafSTom Warren 18999c6bafSTom Warren /* UART configs */ 19999c6bafSTom Warren FUNCMUX_UART1_KBC = 0, 20999c6bafSTom Warren FUNCMUX_UART4_GPIO = 0, 21999c6bafSTom Warren }; 22999c6bafSTom Warren #endif /* _TEGRA124_FUNCMUX_H_ */ 23