1 /* 2 * (C) Copyright 2010-2013 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* Tegra124 clock control definitions */ 9 10 #ifndef _TEGRA124_CLOCK_H_ 11 #define _TEGRA124_CLOCK_H_ 12 13 #include <asm/arch-tegra/clock.h> 14 15 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 16 #define OSC_FREQ_SHIFT 28 17 #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 18 19 /* CLK_RST_CONTROLLER_PLLC_MISC_0 */ 20 #define PLLC_IDDQ (1 << 26) 21 22 /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ 23 #define SOR0_CLK_SEL0 (1 << 14) 24 #define SOR0_CLK_SEL1 (1 << 15) 25 26 int tegra_plle_enable(void); 27 28 void clock_sor_enable_edp_clock(void); 29 30 /** 31 * clock_set_display_rate() - Set the display clock rate 32 * 33 * @frequency: the requested PLLD frequency 34 * 35 * Return the PLLD frequenc (which may not quite what was requested), or 0 36 * on failure 37 */ 38 u32 clock_set_display_rate(u32 frequency); 39 40 /** 41 * clock_set_up_plldp() - Set up the EDP clock ready for use 42 */ 43 void clock_set_up_plldp(void); 44 45 #endif /* _TEGRA124_CLOCK_H_ */ 46