1999c6bafSTom Warren /* 2999c6bafSTom Warren * (C) Copyright 2010-2013 3999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 4999c6bafSTom Warren * 5999c6bafSTom Warren * SPDX-License-Identifier: GPL-2.0+ 6999c6bafSTom Warren */ 7999c6bafSTom Warren 8999c6bafSTom Warren /* Tegra124 clock control definitions */ 9999c6bafSTom Warren 10999c6bafSTom Warren #ifndef _TEGRA124_CLOCK_H_ 11999c6bafSTom Warren #define _TEGRA124_CLOCK_H_ 12999c6bafSTom Warren 13999c6bafSTom Warren #include <asm/arch-tegra/clock.h> 14999c6bafSTom Warren 15999c6bafSTom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 16999c6bafSTom Warren #define OSC_FREQ_SHIFT 28 17999c6bafSTom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 18999c6bafSTom Warren 19*aba11d44SThierry Reding /* CLK_RST_CONTROLLER_PLLC_MISC_0 */ 20*aba11d44SThierry Reding #define PLLC_IDDQ (1 << 26) 21*aba11d44SThierry Reding 2296e82a25SSimon Glass /* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */ 2396e82a25SSimon Glass #define SOR0_CLK_SEL0 (1 << 14) 2496e82a25SSimon Glass #define SOR0_CLK_SEL1 (1 << 15) 2596e82a25SSimon Glass 26a7230745SThierry Reding int tegra_plle_enable(void); 27a7230745SThierry Reding 2896e82a25SSimon Glass void clock_sor_enable_edp_clock(void); 2996e82a25SSimon Glass 3096e82a25SSimon Glass /** 3196e82a25SSimon Glass * clock_set_display_rate() - Set the display clock rate 3296e82a25SSimon Glass * 3396e82a25SSimon Glass * @frequency: the requested PLLD frequency 3496e82a25SSimon Glass * 3596e82a25SSimon Glass * Return the PLLD frequenc (which may not quite what was requested), or 0 3696e82a25SSimon Glass * on failure 3796e82a25SSimon Glass */ 3896e82a25SSimon Glass u32 clock_set_display_rate(u32 frequency); 3996e82a25SSimon Glass 4096e82a25SSimon Glass /** 4196e82a25SSimon Glass * clock_set_up_plldp() - Set up the EDP clock ready for use 4296e82a25SSimon Glass */ 4396e82a25SSimon Glass void clock_set_up_plldp(void); 4496e82a25SSimon Glass 45999c6bafSTom Warren #endif /* _TEGRA124_CLOCK_H_ */ 46