1999c6bafSTom Warren /* 2999c6bafSTom Warren * (C) Copyright 2010-2013 3999c6bafSTom Warren * NVIDIA Corporation <www.nvidia.com> 4999c6bafSTom Warren * 5999c6bafSTom Warren * SPDX-License-Identifier: GPL-2.0+ 6999c6bafSTom Warren */ 7999c6bafSTom Warren 8999c6bafSTom Warren /* Tegra124 clock control definitions */ 9999c6bafSTom Warren 10999c6bafSTom Warren #ifndef _TEGRA124_CLOCK_H_ 11999c6bafSTom Warren #define _TEGRA124_CLOCK_H_ 12999c6bafSTom Warren 13999c6bafSTom Warren #include <asm/arch-tegra/clock.h> 14999c6bafSTom Warren 15999c6bafSTom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 16999c6bafSTom Warren #define OSC_FREQ_SHIFT 28 17999c6bafSTom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 18999c6bafSTom Warren 19*a7230745SThierry Reding int tegra_plle_enable(void); 20*a7230745SThierry Reding 21999c6bafSTom Warren #endif /* _TEGRA124_CLOCK_H_ */ 22