1 /* 2 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _TEGRA114_SYSCTR_H_ 18 #define _TEGRA114_SYSCTR_H_ 19 20 struct sysctr_ctlr { 21 u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ 22 u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ 23 u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ 24 u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ 25 u32 reserved1[4]; /* 0x10 - 0x1C */ 26 u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ 27 u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ 28 u32 reserved2[1002]; /* 0x28 - 0xFCC */ 29 u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ 30 }; 31 32 #define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ 33 #define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ 34 35 #endif /* _TEGRA114_SYSCTR_H_ */ 36