1 /*
2  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms and conditions of the GNU General Public License,
6  * version 2, as published by the Free Software Foundation.
7  *
8  * This program is distributed in the hope it will be useful, but WITHOUT
9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11  * more details.
12  *
13  * You should have received a copy of the GNU General Public License
14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15  */
16 
17 #ifndef _TEGRA114_PINMUX_H_
18 #define _TEGRA114_PINMUX_H_
19 
20 /*
21  * Pin groups which we adjust. There are three basic attributes of each pin
22  * group which use this enum:
23  *
24  *	- function
25  *	- pullup / pulldown
26  *	- tristate or normal
27  */
28 enum pmux_pingrp {
29 	PINGRP_ULPI_DATA0 = 0,  /* offset 0x3000 */
30 	PINGRP_ULPI_DATA1,
31 	PINGRP_ULPI_DATA2,
32 	PINGRP_ULPI_DATA3,
33 	PINGRP_ULPI_DATA4,
34 	PINGRP_ULPI_DATA5,
35 	PINGRP_ULPI_DATA6,
36 	PINGRP_ULPI_DATA7,
37 	PINGRP_ULPI_CLK,
38 	PINGRP_ULPI_DIR,
39 	PINGRP_ULPI_NXT,
40 	PINGRP_ULPI_STP,
41 	PINGRP_DAP3_FS,
42 	PINGRP_DAP3_DIN,
43 	PINGRP_DAP3_DOUT,
44 	PINGRP_DAP3_SCLK,
45 	PINGRP_GPIO_PV0,
46 	PINGRP_GPIO_PV1,
47 	PINGRP_SDMMC1_CLK,
48 	PINGRP_SDMMC1_CMD,
49 	PINGRP_SDMMC1_DAT3,
50 	PINGRP_SDMMC1_DAT2,
51 	PINGRP_SDMMC1_DAT1,
52 	PINGRP_SDMMC1_DAT0,
53 	PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
54 	PINGRP_CLK2_REQ,
55 	PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
56 	PINGRP_DDC_SCL,
57 	PINGRP_DDC_SDA,
58 	PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
59 	PINGRP_UART2_TXD,
60 	PINGRP_UART2_RTS_N,
61 	PINGRP_UART2_CTS_N,
62 	PINGRP_UART3_TXD,
63 	PINGRP_UART3_RXD,
64 	PINGRP_UART3_CTS_N,
65 	PINGRP_UART3_RTS_N,
66 	PINGRP_GPIO_PU0,
67 	PINGRP_GPIO_PU1,
68 	PINGRP_GPIO_PU2,
69 	PINGRP_GPIO_PU3,
70 	PINGRP_GPIO_PU4,
71 	PINGRP_GPIO_PU5,
72 	PINGRP_GPIO_PU6,
73 	PINGRP_GEN1_I2C_SDA,
74 	PINGRP_GEN1_I2C_SCL,
75 	PINGRP_DAP4_FS,
76 	PINGRP_DAP4_DIN,
77 	PINGRP_DAP4_DOUT,
78 	PINGRP_DAP4_SCLK,
79 	PINGRP_CLK3_OUT,
80 	PINGRP_CLK3_REQ,
81 	PINGRP_GMI_WP_N,
82 	PINGRP_GMI_IORDY,
83 	PINGRP_GMI_WAIT,
84 	PINGRP_GMI_ADV_N,
85 	PINGRP_GMI_CLK,
86 	PINGRP_GMI_CS0_N,
87 	PINGRP_GMI_CS1_N,
88 	PINGRP_GMI_CS2_N,
89 	PINGRP_GMI_CS3_N,
90 	PINGRP_GMI_CS4_N,
91 	PINGRP_GMI_CS6_N,
92 	PINGRP_GMI_CS7_N,
93 	PINGRP_GMI_AD0,
94 	PINGRP_GMI_AD1,
95 	PINGRP_GMI_AD2,
96 	PINGRP_GMI_AD3,
97 	PINGRP_GMI_AD4,
98 	PINGRP_GMI_AD5,
99 	PINGRP_GMI_AD6,
100 	PINGRP_GMI_AD7,
101 	PINGRP_GMI_AD8,
102 	PINGRP_GMI_AD9,
103 	PINGRP_GMI_AD10,
104 	PINGRP_GMI_AD11,
105 	PINGRP_GMI_AD12,
106 	PINGRP_GMI_AD13,
107 	PINGRP_GMI_AD14,
108 	PINGRP_GMI_AD15,
109 	PINGRP_GMI_A16,
110 	PINGRP_GMI_A17,
111 	PINGRP_GMI_A18,
112 	PINGRP_GMI_A19,
113 	PINGRP_GMI_WR_N,
114 	PINGRP_GMI_OE_N,
115 	PINGRP_GMI_DQS,
116 	PINGRP_GMI_RST_N,
117 	PINGRP_GEN2_I2C_SCL,
118 	PINGRP_GEN2_I2C_SDA,
119 	PINGRP_SDMMC4_CLK,
120 	PINGRP_SDMMC4_CMD,
121 	PINGRP_SDMMC4_DAT0,
122 	PINGRP_SDMMC4_DAT1,
123 	PINGRP_SDMMC4_DAT2,
124 	PINGRP_SDMMC4_DAT3,
125 	PINGRP_SDMMC4_DAT4,
126 	PINGRP_SDMMC4_DAT5,
127 	PINGRP_SDMMC4_DAT6,
128 	PINGRP_SDMMC4_DAT7,
129 	PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
130 	PINGRP_GPIO_PCC1,
131 	PINGRP_GPIO_PBB0,
132 	PINGRP_CAM_I2C_SCL,
133 	PINGRP_CAM_I2C_SDA,
134 	PINGRP_GPIO_PBB3,
135 	PINGRP_GPIO_PBB4,
136 	PINGRP_GPIO_PBB5,
137 	PINGRP_GPIO_PBB6,
138 	PINGRP_GPIO_PBB7,
139 	PINGRP_GPIO_PCC2,
140 	PINGRP_JTAG_RTCK,
141 	PINGRP_PWR_I2C_SCL,
142 	PINGRP_PWR_I2C_SDA,
143 	PINGRP_KB_ROW0,
144 	PINGRP_KB_ROW1,
145 	PINGRP_KB_ROW2,
146 	PINGRP_KB_ROW3,
147 	PINGRP_KB_ROW4,
148 	PINGRP_KB_ROW5,
149 	PINGRP_KB_ROW6,
150 	PINGRP_KB_ROW7,
151 	PINGRP_KB_ROW8,
152 	PINGRP_KB_ROW9,
153 	PINGRP_KB_ROW10,
154 	PINGRP_KB_COL0 = PINGRP_KB_ROW10 + 6,
155 	PINGRP_KB_COL1,
156 	PINGRP_KB_COL2,
157 	PINGRP_KB_COL3,
158 	PINGRP_KB_COL4,
159 	PINGRP_KB_COL5,
160 	PINGRP_KB_COL6,
161 	PINGRP_KB_COL7,
162 	PINGRP_CLK_32K_OUT,
163 	PINGRP_SYS_CLK_REQ,
164 	PINGRP_CORE_PWR_REQ,
165 	PINGRP_CPU_PWR_REQ,
166 	PINGRP_PWR_INT_N,
167 	PINGRP_CLK_32K_IN,
168 	PINGRP_OWR,
169 	PINGRP_DAP1_FS,
170 	PINGRP_DAP1_DIN,
171 	PINGRP_DAP1_DOUT,
172 	PINGRP_DAP1_SCLK,
173 	PINGRP_CLK1_REQ,
174 	PINGRP_CLK1_OUT,
175 	PINGRP_SPDIF_IN,
176 	PINGRP_SPDIF_OUT,
177 	PINGRP_DAP2_FS,
178 	PINGRP_DAP2_DIN,
179 	PINGRP_DAP2_DOUT,
180 	PINGRP_DAP2_SCLK,
181 	PINGRP_DVFS_PWM,
182 	PINGRP_GPIO_X1_AUD,
183 	PINGRP_GPIO_X3_AUD,
184 	PINGRP_DVFS_CLK,
185 	PINGRP_GPIO_X4_AUD,
186 	PINGRP_GPIO_X5_AUD,
187 	PINGRP_GPIO_X6_AUD,
188 	PINGRP_GPIO_X7_AUD,
189 	PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
190 	PINGRP_SDMMC3_CMD,
191 	PINGRP_SDMMC3_DAT0,
192 	PINGRP_SDMMC3_DAT1,
193 	PINGRP_SDMMC3_DAT2,
194 	PINGRP_SDMMC3_DAT3,
195 	PINGRP_HDMI_CEC = PINGRP_SDMMC3_DAT3 + 15, /* offset 0x33e0 */
196 	PINGRP_SDMMC1_WP_N,
197 	PINGRP_SDMMC3_CD_N,
198 	PINGRP_GPIO_W2_AUD,
199 	PINGRP_GPIO_W3_AUD,
200 	PINGRP_USB_VBUS_EN0,	/* offset 0x33f4 */
201 	PINGRP_USB_VBUS_EN1,
202 	PINGRP_SDMMC3_CLK_LB_IN,
203 	PINGRP_SDMMC3_CLK_LB_OUT,
204 	PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
205 	PINGRP_COUNT,
206 };
207 
208 enum pdrive_pingrp {
209 	PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
210 	PDRIVE_PINGROUP_AO2,
211 	PDRIVE_PINGROUP_AT1,
212 	PDRIVE_PINGROUP_AT2,
213 	PDRIVE_PINGROUP_AT3,
214 	PDRIVE_PINGROUP_AT4,
215 	PDRIVE_PINGROUP_AT5,
216 	PDRIVE_PINGROUP_CDEV1,
217 	PDRIVE_PINGROUP_CDEV2,
218 	PDRIVE_PINGROUP_DAP1 = 10,	/* offset 0x890 */
219 	PDRIVE_PINGROUP_DAP2,
220 	PDRIVE_PINGROUP_DAP3,
221 	PDRIVE_PINGROUP_DAP4,
222 	PDRIVE_PINGROUP_DBG,
223 	PDRIVE_PINGROUP_SDIO3 = 18,	/* offset 0x8B0 */
224 	PDRIVE_PINGROUP_SPI,
225 	PDRIVE_PINGROUP_UAA,
226 	PDRIVE_PINGROUP_UAB,
227 	PDRIVE_PINGROUP_UART2,
228 	PDRIVE_PINGROUP_UART3,
229 	PDRIVE_PINGROUP_SDIO1 = 33,     /* offset 0x8EC */
230 	PDRIVE_PINGROUP_DDC = 37,       /* offset 0x8FC */
231 	PDRIVE_PINGROUP_GMA,
232 	PDRIVE_PINGROUP_GME = 42,	/* offset 0x910 */
233 	PDRIVE_PINGROUP_GMF,
234 	PDRIVE_PINGROUP_GMG,
235 	PDRIVE_PINGROUP_GMH,
236 	PDRIVE_PINGROUP_OWR,
237 	PDRIVE_PINGROUP_UAD,
238 	PDRIVE_PINGROUP_DEV3 = 49,      /* offset 0x92c */
239 	PDRIVE_PINGROUP_CEC = 52,       /* offset 0x938 */
240 	PDRIVE_PINGROUP_AT6 = 75,	/* offset 0x994 */
241 	PDRIVE_PINGROUP_DAP5,
242 	PDRIVE_PINGROUP_VBUS,
243 	PDRIVE_PINGROUP_AO3,
244 	PDRIVE_PINGROUP_HVC,
245 	PDRIVE_PINGROUP_SDIO4,
246 	PDRIVE_PINGROUP_AO0,
247 	PDRIVE_PINGROUP_COUNT,
248 };
249 
250 /*
251  * Functions which can be assigned to each of the pin groups. The values here
252  * bear no relation to the values programmed into pinmux registers and are
253  * purely a convenience. The translation is done through a table search.
254  */
255 enum pmux_func {
256 	PMUX_FUNC_AHB_CLK,
257 	PMUX_FUNC_APB_CLK,
258 	PMUX_FUNC_AUDIO_SYNC,
259 	PMUX_FUNC_CRT,
260 	PMUX_FUNC_DAP1,
261 	PMUX_FUNC_DAP2,
262 	PMUX_FUNC_DAP3,
263 	PMUX_FUNC_DAP4,
264 	PMUX_FUNC_DAP5,
265 	PMUX_FUNC_DISPA,
266 	PMUX_FUNC_DISPB,
267 	PMUX_FUNC_EMC_TEST0_DLL,
268 	PMUX_FUNC_EMC_TEST1_DLL,
269 	PMUX_FUNC_GMI,
270 	PMUX_FUNC_GMI_INT,
271 	PMUX_FUNC_HDMI,
272 	PMUX_FUNC_I2C1,
273 	PMUX_FUNC_I2C2,
274 	PMUX_FUNC_I2C3,
275 	PMUX_FUNC_IDE,
276 	PMUX_FUNC_KBC,
277 	PMUX_FUNC_MIO,
278 	PMUX_FUNC_MIPI_HS,
279 	PMUX_FUNC_NAND,
280 	PMUX_FUNC_OSC,
281 	PMUX_FUNC_OWR,
282 	PMUX_FUNC_PCIE,
283 	PMUX_FUNC_PLLA_OUT,
284 	PMUX_FUNC_PLLC_OUT1,
285 	PMUX_FUNC_PLLM_OUT1,
286 	PMUX_FUNC_PLLP_OUT2,
287 	PMUX_FUNC_PLLP_OUT3,
288 	PMUX_FUNC_PLLP_OUT4,
289 	PMUX_FUNC_PWM,
290 	PMUX_FUNC_PWR_INTR,
291 	PMUX_FUNC_PWR_ON,
292 	PMUX_FUNC_RTCK,
293 	PMUX_FUNC_SDMMC1,
294 	PMUX_FUNC_SDMMC2,
295 	PMUX_FUNC_SDMMC3,
296 	PMUX_FUNC_SDMMC4,
297 	PMUX_FUNC_SFLASH,
298 	PMUX_FUNC_SPDIF,
299 	PMUX_FUNC_SPI1,
300 	PMUX_FUNC_SPI2,
301 	PMUX_FUNC_SPI2_ALT,
302 	PMUX_FUNC_SPI3,
303 	PMUX_FUNC_SPI4,
304 	PMUX_FUNC_TRACE,
305 	PMUX_FUNC_TWC,
306 	PMUX_FUNC_UARTA,
307 	PMUX_FUNC_UARTB,
308 	PMUX_FUNC_UARTC,
309 	PMUX_FUNC_UARTD,
310 	PMUX_FUNC_UARTE,
311 	PMUX_FUNC_ULPI,
312 	PMUX_FUNC_VI,
313 	PMUX_FUNC_VI_SENSOR_CLK,
314 	PMUX_FUNC_XIO,
315 	/* End of Tegra2 MUX selectors */
316 	PMUX_FUNC_BLINK,
317 	PMUX_FUNC_CEC,
318 	PMUX_FUNC_CLK12,
319 	PMUX_FUNC_DAP,
320 	PMUX_FUNC_DAPSDMMC2,
321 	PMUX_FUNC_DDR,
322 	PMUX_FUNC_DEV3,
323 	PMUX_FUNC_DTV,
324 	PMUX_FUNC_VI_ALT1,
325 	PMUX_FUNC_VI_ALT2,
326 	PMUX_FUNC_VI_ALT3,
327 	PMUX_FUNC_EMC_DLL,
328 	PMUX_FUNC_EXTPERIPH1,
329 	PMUX_FUNC_EXTPERIPH2,
330 	PMUX_FUNC_EXTPERIPH3,
331 	PMUX_FUNC_GMI_ALT,
332 	PMUX_FUNC_HDA,
333 	PMUX_FUNC_HSI,
334 	PMUX_FUNC_I2C4,
335 	PMUX_FUNC_I2C5,
336 	PMUX_FUNC_I2CPWR,
337 	PMUX_FUNC_I2S0,
338 	PMUX_FUNC_I2S1,
339 	PMUX_FUNC_I2S2,
340 	PMUX_FUNC_I2S3,
341 	PMUX_FUNC_I2S4,
342 	PMUX_FUNC_NAND_ALT,
343 	PMUX_FUNC_POPSDIO4,
344 	PMUX_FUNC_POPSDMMC4,
345 	PMUX_FUNC_PWM0,
346 	PMUX_FUNC_PWM1,
347 	PMUX_FUNC_PWM2,
348 	PMUX_FUNC_PWM3,
349 	PMUX_FUNC_SATA,
350 	PMUX_FUNC_SPI5,
351 	PMUX_FUNC_SPI6,
352 	PMUX_FUNC_SYSCLK,
353 	PMUX_FUNC_VGP1,
354 	PMUX_FUNC_VGP2,
355 	PMUX_FUNC_VGP3,
356 	PMUX_FUNC_VGP4,
357 	PMUX_FUNC_VGP5,
358 	PMUX_FUNC_VGP6,
359 	/* End of Tegra3 MUX selectors */
360 	PMUX_FUNC_USB,
361 	PMUX_FUNC_SOC,
362 	PMUX_FUNC_CPU,
363 	PMUX_FUNC_CLK,
364 	PMUX_FUNC_PWRON,
365 	PMUX_FUNC_PMI,
366 	PMUX_FUNC_CLDVFS,
367 	PMUX_FUNC_RESET_OUT_N,
368 	/* End of Tegra114 MUX selectors */
369 
370 	PMUX_FUNC_SAFE,
371 	PMUX_FUNC_MAX,
372 
373 	PMUX_FUNC_INVALID = 0x4000,
374 	PMUX_FUNC_RSVD1 = 0x8000,
375 	PMUX_FUNC_RSVD2 = 0x8001,
376 	PMUX_FUNC_RSVD3 = 0x8002,
377 	PMUX_FUNC_RSVD4 = 0x8003,
378 };
379 
380 /* return 1 if a pmux_func is in range */
381 #define pmux_func_isvalid(func) ((((func) >= 0) && ((func) < PMUX_FUNC_MAX)) \
382 	|| (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
383 
384 /* return 1 if a pingrp is in range */
385 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
386 
387 /* The pullup/pulldown state of a pin group */
388 enum pmux_pull {
389 	PMUX_PULL_NORMAL = 0,
390 	PMUX_PULL_DOWN,
391 	PMUX_PULL_UP,
392 };
393 /* return 1 if a pin_pupd_is in range */
394 #define pmux_pin_pupd_isvalid(pupd) (((pupd) >= PMUX_PULL_NORMAL) && \
395 				((pupd) <= PMUX_PULL_UP))
396 
397 /* Defines whether a pin group is tristated or in normal operation */
398 enum pmux_tristate {
399 	PMUX_TRI_NORMAL = 0,
400 	PMUX_TRI_TRISTATE = 1,
401 };
402 /* return 1 if a pin_tristate_is in range */
403 #define pmux_pin_tristate_isvalid(tristate) (((tristate) >= PMUX_TRI_NORMAL) \
404 				&& ((tristate) <= PMUX_TRI_TRISTATE))
405 
406 enum pmux_pin_io {
407 	PMUX_PIN_OUTPUT = 0,
408 	PMUX_PIN_INPUT = 1,
409 	PMUX_PIN_NONE,
410 };
411 /* return 1 if a pin_io_is in range */
412 #define pmux_pin_io_isvalid(io) (((io) >= PMUX_PIN_OUTPUT) && \
413 				((io) <= PMUX_PIN_INPUT))
414 
415 enum pmux_pin_lock {
416 	PMUX_PIN_LOCK_DEFAULT = 0,
417 	PMUX_PIN_LOCK_DISABLE,
418 	PMUX_PIN_LOCK_ENABLE,
419 };
420 /* return 1 if a pin_lock is in range */
421 #define pmux_pin_lock_isvalid(lock) (((lock) >= PMUX_PIN_LOCK_DEFAULT) && \
422 				((lock) <= PMUX_PIN_LOCK_ENABLE))
423 
424 enum pmux_pin_od {
425 	PMUX_PIN_OD_DEFAULT = 0,
426 	PMUX_PIN_OD_DISABLE,
427 	PMUX_PIN_OD_ENABLE,
428 };
429 /* return 1 if a pin_od is in range */
430 #define pmux_pin_od_isvalid(od) (((od) >= PMUX_PIN_OD_DEFAULT) && \
431 				((od) <= PMUX_PIN_OD_ENABLE))
432 
433 enum pmux_pin_ioreset {
434 	PMUX_PIN_IO_RESET_DEFAULT = 0,
435 	PMUX_PIN_IO_RESET_DISABLE,
436 	PMUX_PIN_IO_RESET_ENABLE,
437 };
438 /* return 1 if a pin_ioreset_is in range */
439 #define pmux_pin_ioreset_isvalid(ioreset) \
440 				(((ioreset) >= PMUX_PIN_IO_RESET_DEFAULT) && \
441 				((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
442 
443 enum pmux_pin_rcv_sel {
444 	PMUX_PIN_RCV_SEL_DEFAULT = 0,
445 	PMUX_PIN_RCV_SEL_NORMAL,
446 	PMUX_PIN_RCV_SEL_HIGH,
447 };
448 /* return 1 if a pin_rcv_sel_is in range */
449 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
450 				(((rcv_sel) >= PMUX_PIN_RCV_SEL_DEFAULT) && \
451 				((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
452 
453 /* Available power domains used by pin groups */
454 enum pmux_vddio {
455 	PMUX_VDDIO_BB = 0,
456 	PMUX_VDDIO_LCD,
457 	PMUX_VDDIO_VI,
458 	PMUX_VDDIO_UART,
459 	PMUX_VDDIO_DDR,
460 	PMUX_VDDIO_NAND,
461 	PMUX_VDDIO_SYS,
462 	PMUX_VDDIO_AUDIO,
463 	PMUX_VDDIO_SD,
464 	PMUX_VDDIO_CAM,
465 	PMUX_VDDIO_GMI,
466 	PMUX_VDDIO_PEXCTL,
467 	PMUX_VDDIO_SDMMC1,
468 	PMUX_VDDIO_SDMMC3,
469 	PMUX_VDDIO_SDMMC4,
470 
471 	PMUX_VDDIO_NONE
472 };
473 
474 #define PGRP_SLWF_NONE	-1
475 #define PGRP_SLWF_MAX	3
476 #define PGRP_SLWR_NONE	PGRP_SLWF_NONE
477 #define PGRP_SLWR_MAX	PGRP_SLWF_MAX
478 
479 #define PGRP_DRVUP_NONE	-1
480 #define PGRP_DRVUP_MAX	127
481 #define PGRP_DRVDN_NONE	PGRP_DRVUP_NONE
482 #define PGRP_DRVDN_MAX	PGRP_DRVUP_MAX
483 
484 #define PGRP_SCHMT_NONE	-1
485 #define PGRP_HSM_NONE	PGRP_SCHMT_NONE
486 
487 /* return 1 if a padgrp is in range */
488 #define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
489 
490 /* return 1 if a slew-rate rising/falling edge value is in range */
491 #define pmux_pad_slw_isvalid(slw) (((slw) == PGRP_SLWF_NONE) || \
492 				(((slw) >= 0) && ((slw) <= PGRP_SLWF_MAX)))
493 
494 /* return 1 if a driver output pull-up/down strength code value is in range */
495 #define pmux_pad_drv_isvalid(drv) (((drv) == PGRP_DRVUP_NONE) || \
496 				(((drv) >= 0) && ((drv) <= PGRP_DRVUP_MAX)))
497 
498 /* return 1 if a low-power mode value is in range */
499 #define pmux_pad_lpmd_isvalid(lpm) (((lpm) == PGRP_LPMD_NONE) || \
500 				(((lpm) >= 0) && ((lpm) <= PGRP_LPMD_X)))
501 
502 /* Defines a pin group cfg's low-power mode select */
503 enum pgrp_lpmd {
504 	PGRP_LPMD_X8 = 0,
505 	PGRP_LPMD_X4,
506 	PGRP_LPMD_X2,
507 	PGRP_LPMD_X,
508 	PGRP_LPMD_NONE = -1,
509 };
510 
511 /* Defines whether a pin group cfg's schmidt is enabled or not */
512 enum pgrp_schmt {
513 	PGRP_SCHMT_DISABLE = 0,
514 	PGRP_SCHMT_ENABLE = 1,
515 };
516 
517 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
518 enum pgrp_hsm {
519 	PGRP_HSM_DISABLE = 0,
520 	PGRP_HSM_ENABLE = 1,
521 };
522 
523 /*
524  * This defines the configuration for a pin group's pad control config
525  */
526 struct padctrl_config {
527 	enum pdrive_pingrp padgrp;	/* pin group PDRIVE_PINGRP_x */
528 	int slwf;			/* falling edge slew         */
529 	int slwr;			/* rising edge slew          */
530 	int drvup;			/* pull-up drive strength    */
531 	int drvdn;			/* pull-down drive strength  */
532 	enum pgrp_lpmd lpmd;		/* low-power mode selection  */
533 	enum pgrp_schmt schmt;		/* schmidt enable            */
534 	enum pgrp_hsm hsm;		/* high-speed mode enable    */
535 };
536 
537 /* t114 pin drive group and pin mux registers */
538 #define PDRIVE_PINGROUP_OFFSET	(0x868 >> 2)
539 #define PMUX_OFFSET	((0x3000 >> 2) - PDRIVE_PINGROUP_OFFSET - \
540 				PDRIVE_PINGROUP_COUNT)
541 struct pmux_tri_ctlr {
542 	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
543 	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
544 	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08   */
545 	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
546 	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
547 	uint pmt_reserved4[4];		/* _TRI_STATE_REG_A/B/C/D in t20 */
548 	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24        */
549 
550 	uint pmt_reserved[528];		/* ABP_MISC_PP_ reserved offs 28-864 */
551 
552 	uint pmt_drive[PDRIVE_PINGROUP_COUNT];	/* pin drive grps offs 868 */
553 	uint pmt_reserved5[PMUX_OFFSET];
554 	uint pmt_ctl[PINGRP_COUNT];	/* mux/pupd/tri regs, offset 0x3000 */
555 };
556 
557 /*
558  * This defines the configuration for a pin, including the function assigned,
559  * pull up/down settings and tristate settings. Having set up one of these
560  * you can call pinmux_config_pingroup() to configure a pin in one step. Also
561  * available is pinmux_config_table() to configure a list of pins.
562  */
563 struct pingroup_config {
564 	enum pmux_pingrp pingroup;	/* pin group PINGRP_...             */
565 	enum pmux_func func;		/* function to assign FUNC_...      */
566 	enum pmux_pull pull;		/* pull up/down/normal PMUX_PULL_...*/
567 	enum pmux_tristate tristate;	/* tristate or normal PMUX_TRI_...  */
568 	enum pmux_pin_io io;		/* input or output PMUX_PIN_...  */
569 	enum pmux_pin_lock lock;	/* lock enable/disable PMUX_PIN...  */
570 	enum pmux_pin_od od;		/* open-drain or push-pull driver  */
571 	enum pmux_pin_ioreset ioreset;	/* input/output reset PMUX_PIN...  */
572 	enum pmux_pin_rcv_sel rcv_sel;	/* select between High and Normal  */
573 					/* VIL/VIH receivers */
574 };
575 
576 /* Set a pin group to tristate */
577 void pinmux_tristate_enable(enum pmux_pingrp pin);
578 
579 /* Set a pin group to normal (non tristate) */
580 void pinmux_tristate_disable(enum pmux_pingrp pin);
581 
582 /* Set the pull up/down feature for a pin group */
583 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd);
584 
585 /* Set the mux function for a pin group */
586 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
587 
588 /* Set the complete configuration for a pin group */
589 void pinmux_config_pingroup(struct pingroup_config *config);
590 
591 /* Set a pin group to tristate or normal */
592 void pinmux_set_tristate(enum pmux_pingrp pin, int enable);
593 
594 /* Set a pin group as input or output */
595 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
596 
597 /**
598  * Configure a list of pin groups
599  *
600  * @param config	List of config items
601  * @param len		Number of config items in list
602  */
603 void pinmux_config_table(struct pingroup_config *config, int len);
604 
605 /* Set a group of pins from a table */
606 void pinmux_init(void);
607 
608 /**
609  * Set the GP pad configs
610  *
611  * @param config	List of config items
612  * @param len		Number of config items in list
613  */
614 void padgrp_config_table(struct padctrl_config *config, int len);
615 
616 #endif	/* _TEGRA114_PINMUX_H_ */
617