1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  *  (C) Copyright 2014
4  *  NVIDIA Corporation <www.nvidia.com>
5  */
6 
7 #ifndef _TEGRA114_MC_H_
8 #define _TEGRA114_MC_H_
9 
10 /**
11  * Defines the memory controller registers we need/care about
12  */
13 struct mc_ctlr {
14 	u32 reserved0[4];			/* offset 0x00 - 0x0C */
15 	u32 mc_smmu_config;			/* offset 0x10 */
16 	u32 mc_smmu_tlb_config;			/* offset 0x14 */
17 	u32 mc_smmu_ptc_config;			/* offset 0x18 */
18 	u32 mc_smmu_ptb_asid;			/* offset 0x1C */
19 	u32 mc_smmu_ptb_data;			/* offset 0x20 */
20 	u32 reserved1[3];			/* offset 0x24 - 0x2C */
21 	u32 mc_smmu_tlb_flush;			/* offset 0x30 */
22 	u32 mc_smmu_ptc_flush;			/* offset 0x34 */
23 	u32 reserved2[6];			/* offset 0x38 - 0x4C */
24 	u32 mc_emem_cfg;			/* offset 0x50 */
25 	u32 mc_emem_adr_cfg;			/* offset 0x54 */
26 	u32 mc_emem_adr_cfg_dev0;		/* offset 0x58 */
27 	u32 mc_emem_adr_cfg_dev1;		/* offset 0x5C */
28 	u32 reserved3[12];			/* offset 0x60 - 0x8C */
29 	u32 mc_emem_arb_reserved[28];		/* offset 0x90 - 0xFC */
30 	u32 reserved4[338];			/* offset 0x100 - 0x644 */
31 	u32 mc_video_protect_bom;		/* offset 0x648 */
32 	u32 mc_video_protect_size_mb;		/* offset 0x64c */
33 	u32 mc_video_protect_reg_ctrl;		/* offset 0x650 */
34 };
35 
36 #endif	/* _TEGRA114_MC_H_ */
37