1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */
22fc65e28STom Warren /*
32fc65e28STom Warren  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
42fc65e28STom Warren  */
52fc65e28STom Warren 
62fc65e28STom Warren #ifndef _TEGRA114_GPIO_H_
72fc65e28STom Warren #define _TEGRA114_GPIO_H_
82fc65e28STom Warren 
92fc65e28STom Warren /*
102fc65e28STom Warren  * The Tegra114 GPIO controller has 246 GPIOS in 8 banks of 4 ports,
112fc65e28STom Warren  * each with 8 GPIOs.
122fc65e28STom Warren  */
132fc65e28STom Warren #define TEGRA_GPIO_PORTS	4	/* number of ports per bank */
142fc65e28STom Warren #define TEGRA_GPIO_BANKS	8	/* number of banks */
152fc65e28STom Warren 
162fc65e28STom Warren #include <asm/arch-tegra/gpio.h>
172fc65e28STom Warren #include <asm/arch-tegra30/gpio.h>
182fc65e28STom Warren 
192fc65e28STom Warren #endif	/* _TEGRA114_GPIO_H_ */
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