1 /* 2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _TEGRA114_GP_PADCTRL_H_ 18 #define _TEGRA114_GP_PADCTRL_H_ 19 20 #include <asm/arch-tegra/gp_padctrl.h> 21 22 /* APB_MISC_GP and padctrl registers */ 23 struct apb_misc_gp_ctlr { 24 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 25 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 26 u32 reserved0[22]; /* 0x08 - 0x5C: */ 27 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 28 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 29 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 30 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ 31 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 32 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 33 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ 34 u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ 35 u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ 36 u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ 37 u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ 38 u32 reserved1; /* 0x8C: */ 39 u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ 40 u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ 41 u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ 42 u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ 43 u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ 44 u32 reserved2[3]; /* 0xA4 - 0xAC: */ 45 u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ 46 u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ 47 u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ 48 u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ 49 u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ 50 u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ 51 u32 reserved3[9]; /* 0xC8-0xE8: */ 52 u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ 53 u32 reserved4[3]; /* 0xF0-0xF8: */ 54 u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ 55 u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ 56 u32 reserved5[3]; /* 0x104-0x10C: */ 57 u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ 58 u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ 59 u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ 60 u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ 61 u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ 62 u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ 63 u32 reserved6; /* 0x128: */ 64 u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ 65 u32 reserved7[2]; /* 0x130 - 0x134: */ 66 u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ 67 u32 reserved8[22]; /* 0x13C - 0x190: */ 68 u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ 69 u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ 70 u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ 71 u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ 72 u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ 73 u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ 74 u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ 75 }; 76 77 /* SDMMC1/3 settings from section 27.5 of T114 TRM */ 78 #define SDIOCFG_DRVUP_SLWF 0 79 #define SDIOCFG_DRVDN_SLWR 0 80 #define SDIOCFG_DRVUP 0x24 81 #define SDIOCFG_DRVDN 0x14 82 83 #endif /* _TEGRA114_GP_PADCTRL_H_ */ 84