1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22fc65e28STom Warren /* 32fc65e28STom Warren * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 42fc65e28STom Warren */ 52fc65e28STom Warren 62fc65e28STom Warren #ifndef _TEGRA114_GP_PADCTRL_H_ 72fc65e28STom Warren #define _TEGRA114_GP_PADCTRL_H_ 82fc65e28STom Warren 92fc65e28STom Warren #include <asm/arch-tegra/gp_padctrl.h> 102fc65e28STom Warren 112fc65e28STom Warren /* APB_MISC_GP and padctrl registers */ 122fc65e28STom Warren struct apb_misc_gp_ctlr { 132fc65e28STom Warren u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */ 142fc65e28STom Warren u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */ 152fc65e28STom Warren u32 reserved0[22]; /* 0x08 - 0x5C: */ 162fc65e28STom Warren u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */ 172fc65e28STom Warren u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */ 182fc65e28STom Warren u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */ 1936c48be1STom Warren u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */ 202fc65e28STom Warren u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */ 212fc65e28STom Warren u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */ 222fc65e28STom Warren u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */ 232fc65e28STom Warren u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */ 242fc65e28STom Warren u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */ 252fc65e28STom Warren u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */ 262fc65e28STom Warren u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */ 2736c48be1STom Warren u32 reserved1; /* 0x8C: */ 282fc65e28STom Warren u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */ 292fc65e28STom Warren u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */ 302fc65e28STom Warren u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */ 312fc65e28STom Warren u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */ 322fc65e28STom Warren u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */ 3336c48be1STom Warren u32 reserved2[3]; /* 0xA4 - 0xAC: */ 342fc65e28STom Warren u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */ 352fc65e28STom Warren u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */ 362fc65e28STom Warren u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */ 372fc65e28STom Warren u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */ 382fc65e28STom Warren u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */ 392fc65e28STom Warren u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */ 4036c48be1STom Warren u32 reserved3[9]; /* 0xC8-0xE8: */ 412fc65e28STom Warren u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */ 4236c48be1STom Warren u32 reserved4[3]; /* 0xF0-0xF8: */ 4336c48be1STom Warren u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */ 4436c48be1STom Warren u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */ 4536c48be1STom Warren u32 reserved5[3]; /* 0x104-0x10C: */ 4636c48be1STom Warren u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */ 4736c48be1STom Warren u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */ 4836c48be1STom Warren u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */ 4936c48be1STom Warren u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */ 5036c48be1STom Warren u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */ 5136c48be1STom Warren u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */ 5236c48be1STom Warren u32 reserved6; /* 0x128: */ 5336c48be1STom Warren u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */ 5436c48be1STom Warren u32 reserved7[2]; /* 0x130 - 0x134: */ 5536c48be1STom Warren u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */ 5636c48be1STom Warren u32 reserved8[22]; /* 0x13C - 0x190: */ 5736c48be1STom Warren u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */ 5836c48be1STom Warren u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */ 5936c48be1STom Warren u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */ 6036c48be1STom Warren u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */ 6136c48be1STom Warren u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */ 6236c48be1STom Warren u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */ 6336c48be1STom Warren u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ 642fc65e28STom Warren }; 652fc65e28STom Warren 662a04a317STom Warren /* SDMMC1/3 settings from section 27.5 of T114 TRM */ 672a04a317STom Warren #define SDIOCFG_DRVUP_SLWF 0 682a04a317STom Warren #define SDIOCFG_DRVDN_SLWR 0 692a04a317STom Warren #define SDIOCFG_DRVUP 0x24 702a04a317STom Warren #define SDIOCFG_DRVDN 0x14 712a04a317STom Warren 722fc65e28STom Warren #endif /* _TEGRA114_GP_PADCTRL_H_ */ 73