1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22fc65e28STom Warren /* 32fc65e28STom Warren * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 42fc65e28STom Warren */ 52fc65e28STom Warren 62fc65e28STom Warren /* Tegra114 high-level function multiplexing */ 72fc65e28STom Warren 82fc65e28STom Warren #ifndef _TEGRA114_FUNCMUX_H_ 92fc65e28STom Warren #define _TEGRA114_FUNCMUX_H_ 102fc65e28STom Warren 112fc65e28STom Warren #include <asm/arch-tegra/funcmux.h> 122fc65e28STom Warren 132fc65e28STom Warren /* Configs supported by the func mux */ 142fc65e28STom Warren enum { 152fc65e28STom Warren FUNCMUX_DEFAULT = 0, /* default config */ 162fc65e28STom Warren 172fc65e28STom Warren /* UART configs */ 182fc65e28STom Warren FUNCMUX_UART4_GMI = 0, 192fc65e28STom Warren }; 202fc65e28STom Warren #endif /* _TEGRA114_FUNCMUX_H_ */ 21