1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 22fc65e28STom Warren /* 32fc65e28STom Warren * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. 42fc65e28STom Warren */ 52fc65e28STom Warren 62fc65e28STom Warren /* Tegra114 clock control functions */ 72fc65e28STom Warren 82fc65e28STom Warren #ifndef _TEGRA114_CLOCK_H_ 92fc65e28STom Warren #define _TEGRA114_CLOCK_H_ 102fc65e28STom Warren 112fc65e28STom Warren #include <asm/arch-tegra/clock.h> 122fc65e28STom Warren 132fc65e28STom Warren /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 142fc65e28STom Warren #define OSC_FREQ_SHIFT 28 152fc65e28STom Warren #define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT) 162fc65e28STom Warren 178e1601d9SThierry Reding /* CLK_RST_CONTROLLER_PLLC_MISC_0 */ 188e1601d9SThierry Reding #define PLLC_IDDQ (1 << 26) 198e1601d9SThierry Reding 202fc65e28STom Warren #endif /* _TEGRA114_CLOCK_H_ */ 21