1 /* 2 * (C) Copyright 2010, 2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _WARM_BOOT_H_ 25 #define _WARM_BOOT_H_ 26 27 #define STRAP_OPT_A_RAM_CODE_SHIFT 4 28 #define STRAP_OPT_A_RAM_CODE_MASK (0xf << STRAP_OPT_A_RAM_CODE_SHIFT) 29 30 /* Defines the supported operating modes */ 31 enum fuse_operating_mode { 32 MODE_PRODUCTION = 3, 33 MODE_UNDEFINED, 34 }; 35 36 /* Defines the CMAC-AES-128 hash length in 32 bit words. (128 bits = 4 words) */ 37 enum { 38 HASH_LENGTH = 4 39 }; 40 41 /* Defines the storage for a hash value (128 bits) */ 42 struct hash { 43 u32 hash[HASH_LENGTH]; 44 }; 45 46 /* 47 * Defines the code header information for the boot rom. 48 * 49 * The code immediately follows the code header. 50 * 51 * Note that the code header needs to be 16 bytes aligned to preserve 52 * the alignment of relevant data for hash and decryption computations without 53 * requiring extra copies to temporary memory areas. 54 */ 55 struct wb_header { 56 u32 length_insecure; /* length of the code header */ 57 u32 reserved[3]; 58 struct hash hash; /* hash of header+code, starts next field*/ 59 struct hash random_aes_block; /* a data block to aid security. */ 60 u32 length_secure; /* length of the code header */ 61 u32 destination; /* destination address to put the wb code */ 62 u32 entry_point; /* execution address of the wb code */ 63 u32 code_length; /* length of the code */ 64 }; 65 66 /* 67 * The warm boot code needs direct access to these registers since it runs in 68 * SRAM and cannot call other U-Boot code. 69 */ 70 union osc_ctrl_reg { 71 struct { 72 u32 xoe:1; 73 u32 xobp:1; 74 u32 reserved0:2; 75 u32 xofs:6; 76 u32 reserved1:2; 77 u32 xods:5; 78 u32 reserved2:3; 79 u32 oscfi_spare:8; 80 u32 pll_ref_div:2; 81 u32 osc_freq:2; 82 }; 83 u32 word; 84 }; 85 86 union pllx_base_reg { 87 struct { 88 u32 divm:5; 89 u32 reserved0:3; 90 u32 divn:10; 91 u32 reserved1:2; 92 u32 divp:3; 93 u32 reserved2:4; 94 u32 lock:1; 95 u32 reserved3:1; 96 u32 ref_dis:1; 97 u32 enable:1; 98 u32 bypass:1; 99 }; 100 u32 word; 101 }; 102 103 union pllx_misc_reg { 104 struct { 105 u32 vcocon:4; 106 u32 lfcon:4; 107 u32 cpcon:4; 108 u32 lock_sel:6; 109 u32 reserved0:1; 110 u32 lock_enable:1; 111 u32 reserved1:1; 112 u32 dccon:1; 113 u32 pts:2; 114 u32 reserved2:6; 115 u32 out1_div_byp:1; 116 u32 out1_inv_clk:1; 117 }; 118 u32 word; 119 }; 120 121 /* 122 * TODO: This register is not documented in the TRM yet. We could move this 123 * into the EMC and give it a proper interface, but not while it is 124 * undocumented. 125 */ 126 union scratch3_reg { 127 struct { 128 u32 pllx_base_divm:5; 129 u32 pllx_base_divn:10; 130 u32 pllx_base_divp:3; 131 u32 pllx_misc_lfcon:4; 132 u32 pllx_misc_cpcon:4; 133 }; 134 u32 word; 135 }; 136 137 138 /** 139 * Save warmboot memory settings for a later resume 140 * 141 * @return 0 if ok, -1 on error 142 */ 143 int warmboot_save_sdram_params(void); 144 145 int warmboot_prepare_code(u32 seg_address, u32 seg_length); 146 int sign_data_block(u8 *source, u32 length, u8 *signature); 147 void wb_start(void); /* Start of WB assembly code */ 148 void wb_end(void); /* End of WB assembly code */ 149 150 #endif 151