1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 #ifndef _TEGRA_USB_H_ 23 #define _TEGRA_USB_H_ 24 25 26 /* USB Controller (USBx_CONTROLLER_) regs */ 27 struct usb_ctlr { 28 /* 0x000 */ 29 uint id; 30 uint reserved0; 31 uint host; 32 uint device; 33 34 /* 0x010 */ 35 uint txbuf; 36 uint rxbuf; 37 uint reserved1[2]; 38 39 /* 0x020 */ 40 uint reserved2[56]; 41 42 /* 0x100 */ 43 u16 cap_length; 44 u16 hci_version; 45 uint hcs_params; 46 uint hcc_params; 47 uint reserved3[5]; 48 49 /* 0x120 */ 50 uint dci_version; 51 uint dcc_params; 52 uint reserved4[6]; 53 54 /* 0x140 */ 55 uint usb_cmd; 56 uint usb_sts; 57 uint usb_intr; 58 uint frindex; 59 60 /* 0x150 */ 61 uint reserved5; 62 uint periodic_list_base; 63 uint async_list_addr; 64 uint async_tt_sts; 65 66 /* 0x160 */ 67 uint burst_size; 68 uint tx_fill_tuning; 69 uint reserved6; /* is this port_sc1 on some controllers? */ 70 uint icusb_ctrl; 71 72 /* 0x170 */ 73 uint ulpi_viewport; 74 uint reserved7; 75 uint endpt_nak; 76 uint endpt_nak_enable; 77 78 /* 0x180 */ 79 uint reserved; 80 uint port_sc1; 81 uint reserved8[6]; 82 83 /* 0x1a0 */ 84 uint reserved9; 85 uint otgsc; 86 uint usb_mode; 87 uint endpt_setup_stat; 88 89 /* 0x1b0 */ 90 uint reserved10[20]; 91 92 /* 0x200 */ 93 uint reserved11[0x80]; 94 95 /* 0x400 */ 96 uint susp_ctrl; 97 uint phy_vbus_sensors; 98 uint phy_vbus_wakeup_id; 99 uint phy_alt_vbus_sys; 100 101 /* 0x410 */ 102 uint usb1_legacy_ctrl; 103 uint reserved12[4]; 104 105 /* 0x424 */ 106 uint ulpi_timing_ctrl_0; 107 uint ulpi_timing_ctrl_1; 108 uint reserved13[53]; 109 110 /* 0x500 */ 111 uint reserved14[64 * 3]; 112 113 /* 0x800 */ 114 uint utmip_pll_cfg0; 115 uint utmip_pll_cfg1; 116 uint utmip_xcvr_cfg0; 117 uint utmip_bias_cfg0; 118 119 /* 0x810 */ 120 uint utmip_hsrx_cfg0; 121 uint utmip_hsrx_cfg1; 122 uint utmip_fslsrx_cfg0; 123 uint utmip_fslsrx_cfg1; 124 125 /* 0x820 */ 126 uint utmip_tx_cfg0; 127 uint utmip_misc_cfg0; 128 uint utmip_misc_cfg1; 129 uint utmip_debounce_cfg0; 130 131 /* 0x830 */ 132 uint utmip_bat_chrg_cfg0; 133 uint utmip_spare_cfg0; 134 uint utmip_xcvr_cfg1; 135 uint utmip_bias_cfg1; 136 }; 137 138 139 /* USB1_LEGACY_CTRL */ 140 #define USB1_NO_LEGACY_MODE 1 141 142 #define VBUS_SENSE_CTL_SHIFT 1 143 #define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) 144 #define VBUS_SENSE_CTL_VBUS_WAKEUP 0 145 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 146 #define VBUS_SENSE_CTL_AB_SESS_VLD 2 147 #define VBUS_SENSE_CTL_A_SESS_VLD 3 148 149 /* USB2_IF_ULPI_TIMING_CTRL_0 */ 150 #define ULPI_OUTPUT_PINMUX_BYP (1 << 10) 151 #define ULPI_CLKOUT_PINMUX_BYP (1 << 11) 152 153 /* USB2_IF_ULPI_TIMING_CTRL_1 */ 154 #define ULPI_DATA_TRIMMER_LOAD (1 << 0) 155 #define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1) 156 #define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16) 157 #define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17) 158 #define ULPI_DIR_TRIMMER_LOAD (1 << 24) 159 #define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25) 160 161 /* USBx_IF_USB_SUSP_CTRL_0 */ 162 #define ULPI_PHY_ENB (1 << 13) 163 #define UTMIP_PHY_ENB (1 << 12) 164 #define UTMIP_RESET (1 << 11) 165 #define USB_PHY_CLK_VALID (1 << 7) 166 #define USB_SUSP_CLR (1 << 5) 167 168 /* USBx_UTMIP_MISC_CFG1 */ 169 #define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 170 #define UTMIP_PLLU_STABLE_COUNT_MASK \ 171 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) 172 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 173 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ 174 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) 175 #define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) 176 177 /* USBx_UTMIP_PLL_CFG1_0 */ 178 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 179 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ 180 (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) 181 #define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 182 #define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff 183 184 /* USBx_UTMIP_BIAS_CFG1_0 */ 185 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 186 #define UTMIP_BIAS_PDTRK_COUNT_MASK \ 187 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) 188 189 #define UTMIP_DEBOUNCE_CFG0_SHIFT 0 190 #define UTMIP_DEBOUNCE_CFG0_MASK 0xffff 191 192 /* USBx_UTMIP_TX_CFG0_0 */ 193 #define UTMIP_FS_PREAMBLE_J (1 << 19) 194 195 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */ 196 #define UTMIP_PD_CHRG 1 197 198 /* USBx_UTMIP_XCVR_CFG0_0 */ 199 #define UTMIP_XCVR_LSBIAS_SE (1 << 21) 200 201 /* USBx_UTMIP_SPARE_CFG0_0 */ 202 #define FUSE_SETUP_SEL (1 << 3) 203 204 /* USBx_UTMIP_HSRX_CFG0_0 */ 205 #define UTMIP_IDLE_WAIT_SHIFT 15 206 #define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) 207 #define UTMIP_ELASTIC_LIMIT_SHIFT 10 208 #define UTMIP_ELASTIC_LIMIT_MASK \ 209 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) 210 211 /* USBx_UTMIP_HSRX_CFG0_1 */ 212 #define UTMIP_HS_SYNC_START_DLY_SHIFT 1 213 #define UTMIP_HS_SYNC_START_DLY_MASK \ 214 (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) 215 216 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ 217 #define IC_ENB1 (1 << 3) 218 219 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ 220 #define PTS_SHIFT 30 221 #define PTS_MASK (3U << PTS_SHIFT) 222 #define PTS_UTMI 0 223 #define PTS_RESERVED 1 224 #define PTS_ULPI 2 225 #define PTS_ICUSB_SER 3 226 227 #define STS (1 << 29) 228 #define WKOC (1 << 22) 229 #define WKDS (1 << 21) 230 #define WKCN (1 << 20) 231 232 /* USBx_UTMIP_XCVR_CFG0_0 */ 233 #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) 234 #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) 235 #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) 236 237 /* USBx_UTMIP_XCVR_CFG1_0 */ 238 #define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) 239 #define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) 240 #define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) 241 242 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ 243 #define VBUS_VLD_STS (1 << 26) 244 245 246 /* Setup USB on the board */ 247 int board_usb_init(const void *blob); 248 249 #endif /* _TEGRA_USB_H_ */ 250