1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _UART_H_ 9 #define _UART_H_ 10 11 /* UART registers */ 12 struct uart_ctlr { 13 uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */ 14 uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */ 15 uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */ 16 uint uart_lcr; /* UART_LCR_0, offset 0C */ 17 uint uart_mcr; /* UART_MCR_0, offset 10 */ 18 uint uart_lsr; /* UART_LSR_0, offset 14 */ 19 uint uart_msr; /* UART_MSR_0, offset 18 */ 20 uint uart_spr; /* UART_SPR_0, offset 1C */ 21 uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */ 22 uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/ 23 uint uart_asr; /* UART_ASR_0, offset 3C */ 24 }; 25 26 #define NVRM_PLLP_FIXED_FREQ_KHZ 216000 27 #define NV_DEFAULT_DEBUG_BAUD 115200 28 29 #define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */ 30 31 #endif /* UART_H */ 32