1 /*
2  * (C) Copyright 2010-2015
3  * NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _TEGRA_H_
9 #define _TEGRA_H_
10 
11 #define NV_PA_ARM_PERIPHBASE	0x50040000
12 #define NV_PA_PG_UP_BASE	0x60000000
13 #define NV_PA_TMRUS_BASE	0x60005010
14 #define NV_PA_CLK_RST_BASE	0x60006000
15 #define NV_PA_FLOW_BASE		0x60007000
16 #define NV_PA_GPIO_BASE		0x6000D000
17 #define NV_PA_EVP_BASE		0x6000F000
18 #define NV_PA_APB_MISC_BASE	0x70000000
19 #define NV_PA_APB_MISC_GP_BASE	(NV_PA_APB_MISC_BASE + 0x0800)
20 #define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
21 #define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
22 #define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
23 #define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
24 #define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
25 #define NV_PA_NAND_BASE		(NV_PA_APB_MISC_BASE + 0x8000)
26 #define NV_PA_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
27 #define NV_PA_SLINK1_BASE	(NV_PA_APB_MISC_BASE + 0xD400)
28 #define NV_PA_SLINK2_BASE	(NV_PA_APB_MISC_BASE + 0xD600)
29 #define NV_PA_SLINK3_BASE	(NV_PA_APB_MISC_BASE + 0xD800)
30 #define NV_PA_SLINK4_BASE	(NV_PA_APB_MISC_BASE + 0xDA00)
31 #define NV_PA_SLINK5_BASE	(NV_PA_APB_MISC_BASE + 0xDC00)
32 #define NV_PA_SLINK6_BASE	(NV_PA_APB_MISC_BASE + 0xDE00)
33 #define TEGRA_DVC_BASE		(NV_PA_APB_MISC_BASE + 0xD000)
34 #define NV_PA_PMC_BASE		(NV_PA_APB_MISC_BASE + 0xE400)
35 #define NV_PA_EMC_BASE		(NV_PA_APB_MISC_BASE + 0xF400)
36 #define NV_PA_FUSE_BASE		(NV_PA_APB_MISC_BASE + 0xF800)
37 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
38 	defined(CONFIG_TEGRA114)
39 #define NV_PA_CSITE_BASE	0x70040000
40 #else
41 #define NV_PA_CSITE_BASE	0x70800000
42 #endif
43 #define TEGRA_USB_ADDR_MASK	0xFFFFC000
44 
45 #define NV_PA_SDRC_CS0		NV_PA_SDRAM_BASE
46 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC
47 #define EARLY_AVP_STACK		(NV_PA_SDRAM_BASE + 0x20000)
48 #define EARLY_CPU_STACK		(EARLY_AVP_STACK - 4096)
49 #define PG_UP_TAG_AVP		0xAAAAAAAA
50 
51 #ifndef __ASSEMBLY__
52 struct timerus {
53 	unsigned int cntr_1us;
54 };
55 
56 /* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
57 #define NV_WB_RUN_ADDRESS	0x40020000
58 
59 #define NVBOOTTYPE_RECOVERY	2	/* BR entered RCM */
60 #define NVBOOTINFOTABLE_BOOTTYPE 0xC	/* Boot type in BIT in IRAM */
61 #define NVBOOTINFOTABLE_BCTSIZE	0x38	/* BCT size in BIT in IRAM */
62 #define NVBOOTINFOTABLE_BCTPTR	0x3C	/* BCT pointer in BIT in IRAM */
63 
64 /* These are the available SKUs (product types) for Tegra */
65 enum {
66 	SKU_ID_T20_7		= 0x7,
67 	SKU_ID_T20		= 0x8,
68 	SKU_ID_T25SE		= 0x14,
69 	SKU_ID_AP25		= 0x17,
70 	SKU_ID_T25		= 0x18,
71 	SKU_ID_AP25E		= 0x1b,
72 	SKU_ID_T25E		= 0x1c,
73 	SKU_ID_T33		= 0x80,
74 	SKU_ID_T30		= 0x81, /* Cardhu value */
75 	SKU_ID_TM30MQS_P_A3	= 0xb1,
76 	SKU_ID_T114_ENG		= 0x00, /* Dalmore value, unfused */
77 	SKU_ID_T114_1		= 0x01,
78 	SKU_ID_T124_ENG		= 0x00, /* Venice2 value, unfused */
79 	SKU_ID_T210_ENG		= 0x00, /* unfused value TBD */
80 };
81 
82 /*
83  * These are used to distinguish SOC types for setting up clocks. Mostly
84  * we can tell the clocking required by looking at the SOC sku_id, but
85  * for T30 it is a user option as to whether to run PLLP in fast or slow
86  * mode, so we have two options there.
87  */
88 enum {
89 	TEGRA_SOC_T20,
90 	TEGRA_SOC_T25,
91 	TEGRA_SOC_T30,
92 	TEGRA_SOC_T114,
93 	TEGRA_SOC_T124,
94 	TEGRA_SOC_T210,
95 
96 	TEGRA_SOC_CNT,
97 	TEGRA_SOC_UNKNOWN	= -1,
98 };
99 
100 /* Tegra system controller (SYSCON) devices */
101 enum {
102 	TEGRA_SYSCON_PMC,
103 };
104 
105 #else  /* __ASSEMBLY__ */
106 #define PRM_RSTCTRL		NV_PA_PMC_BASE
107 #endif
108 
109 #endif	/* TEGRA_H */
110