1 /*
2  *  (C) Copyright 2010,2011
3  *  NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _SCU_H_
9 #define _SCU_H_
10 
11 /* ARM Snoop Control Unit (SCU) registers */
12 struct scu_ctlr {
13 	uint scu_ctrl;		/* SCU Control Register, offset 00 */
14 	uint scu_cfg;		/* SCU Config Register, offset 04 */
15 	uint scu_cpu_pwr_stat;	/* SCU CPU Power Status Register, offset 08 */
16 	uint scu_inv_all;	/* SCU Invalidate All Register, offset 0C */
17 	uint scu_reserved0[12];	/* reserved, offset 10-3C */
18 	uint scu_filt_start;	/* SCU Filtering Start Address Reg, offset 40 */
19 	uint scu_filt_end;	/* SCU Filtering End Address Reg, offset 44 */
20 	uint scu_reserved1[2];	/* reserved, offset 48-4C */
21 	uint scu_acc_ctl;	/* SCU Access Control Register, offset 50 */
22 	uint scu_ns_acc_ctl;	/* SCU Non-secure Access Cntrl Reg, offset 54 */
23 };
24 
25 #define SCU_CTRL_ENABLE		(1 << 0)
26 
27 #endif	/* SCU_H */
28