1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <asm/arch/tegra.h> 12 13 /* The pullup/pulldown state of a pin group */ 14 enum pmux_pull { 15 PMUX_PULL_NORMAL = 0, 16 PMUX_PULL_DOWN, 17 PMUX_PULL_UP, 18 }; 19 20 /* Defines whether a pin group is tristated or in normal operation */ 21 enum pmux_tristate { 22 PMUX_TRI_NORMAL = 0, 23 PMUX_TRI_TRISTATE = 1, 24 }; 25 26 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 27 enum pmux_pin_io { 28 PMUX_PIN_OUTPUT = 0, 29 PMUX_PIN_INPUT = 1, 30 PMUX_PIN_NONE, 31 }; 32 #endif 33 34 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 35 enum pmux_pin_lock { 36 PMUX_PIN_LOCK_DEFAULT = 0, 37 PMUX_PIN_LOCK_DISABLE, 38 PMUX_PIN_LOCK_ENABLE, 39 }; 40 #endif 41 42 #ifdef TEGRA_PMX_PINS_HAVE_OD 43 enum pmux_pin_od { 44 PMUX_PIN_OD_DEFAULT = 0, 45 PMUX_PIN_OD_DISABLE, 46 PMUX_PIN_OD_ENABLE, 47 }; 48 #endif 49 50 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 51 enum pmux_pin_ioreset { 52 PMUX_PIN_IO_RESET_DEFAULT = 0, 53 PMUX_PIN_IO_RESET_DISABLE, 54 PMUX_PIN_IO_RESET_ENABLE, 55 }; 56 #endif 57 58 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 59 enum pmux_pin_rcv_sel { 60 PMUX_PIN_RCV_SEL_DEFAULT = 0, 61 PMUX_PIN_RCV_SEL_NORMAL, 62 PMUX_PIN_RCV_SEL_HIGH, 63 }; 64 #endif 65 66 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 67 /* Defines a pin group cfg's low-power mode select */ 68 enum pmux_lpmd { 69 PMUX_LPMD_X8 = 0, 70 PMUX_LPMD_X4, 71 PMUX_LPMD_X2, 72 PMUX_LPMD_X, 73 PMUX_LPMD_NONE = -1, 74 }; 75 #endif 76 77 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) 78 /* Defines whether a pin group cfg's schmidt is enabled or not */ 79 enum pmux_schmt { 80 PMUX_SCHMT_DISABLE = 0, 81 PMUX_SCHMT_ENABLE = 1, 82 PMUX_SCHMT_NONE = -1, 83 }; 84 #endif 85 86 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) 87 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 88 enum pmux_hsm { 89 PMUX_HSM_DISABLE = 0, 90 PMUX_HSM_ENABLE = 1, 91 PMUX_HSM_NONE = -1, 92 }; 93 #endif 94 95 /* 96 * This defines the configuration for a pin, including the function assigned, 97 * pull up/down settings and tristate settings. Having set up one of these 98 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 99 * available is pinmux_config_table() to configure a list of pins. 100 */ 101 struct pmux_pingrp_config { 102 u32 pingrp:16; /* pin group PMUX_PINGRP_... */ 103 u32 func:8; /* function to assign PMUX_FUNC_... */ 104 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ 105 u32 tristate:2; /* tristate or normal PMUX_TRI_... */ 106 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 107 u32 io:2; /* input or output PMUX_PIN_... */ 108 #endif 109 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 110 u32 lock:2; /* lock enable/disable PMUX_PIN... */ 111 #endif 112 #ifdef TEGRA_PMX_PINS_HAVE_OD 113 u32 od:2; /* open-drain or push-pull driver */ 114 #endif 115 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 116 u32 ioreset:2; /* input/output reset PMUX_PIN... */ 117 #endif 118 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 119 u32 rcv_sel:2; /* select between High and Normal */ 120 /* VIL/VIH receivers */ 121 #endif 122 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT 123 u32 schmt:2; /* schmitt enable */ 124 #endif 125 #ifdef TEGRA_PMX_PINS_HAVE_HSM 126 u32 hsm:2; /* high-speed mode enable */ 127 #endif 128 }; 129 130 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING 131 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ 132 void pinmux_set_tristate_input_clamping(void); 133 void pinmux_clear_tristate_input_clamping(void); 134 #endif 135 136 /* Set the mux function for a pin group */ 137 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 138 139 /* Set the pull up/down feature for a pin group */ 140 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 141 142 /* Set a pin group to tristate */ 143 void pinmux_tristate_enable(enum pmux_pingrp pin); 144 145 /* Set a pin group to normal (non tristate) */ 146 void pinmux_tristate_disable(enum pmux_pingrp pin); 147 148 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 149 /* Set a pin group as input or output */ 150 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 151 #endif 152 153 /** 154 * Configure a list of pin groups 155 * 156 * @param config List of config items 157 * @param len Number of config items in list 158 */ 159 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, 160 int len); 161 162 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS 163 164 #define PMUX_SLWF_MIN 0 165 #define PMUX_SLWF_MAX 3 166 #define PMUX_SLWF_NONE -1 167 168 #define PMUX_SLWR_MIN 0 169 #define PMUX_SLWR_MAX 3 170 #define PMUX_SLWR_NONE -1 171 172 #define PMUX_DRVUP_MIN 0 173 #define PMUX_DRVUP_MAX 127 174 #define PMUX_DRVUP_NONE -1 175 176 #define PMUX_DRVDN_MIN 0 177 #define PMUX_DRVDN_MAX 127 178 #define PMUX_DRVDN_NONE -1 179 180 /* 181 * This defines the configuration for a pin group's pad control config 182 */ 183 struct pmux_drvgrp_config { 184 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ 185 u32 slwf:3; /* falling edge slew */ 186 u32 slwr:3; /* rising edge slew */ 187 u32 drvup:8; /* pull-up drive strength */ 188 u32 drvdn:8; /* pull-down drive strength */ 189 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 190 u32 lpmd:3; /* low-power mode selection */ 191 #endif 192 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT 193 u32 schmt:2; /* schmidt enable */ 194 #endif 195 #ifdef TEGRA_PMX_GRPS_HAVE_HSM 196 u32 hsm:2; /* high-speed mode enable */ 197 #endif 198 }; 199 200 /** 201 * Set the GP pad configs 202 * 203 * @param config List of config items 204 * @param len Number of config items in list 205 */ 206 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, 207 int len); 208 209 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ 210 211 struct pmux_pingrp_desc { 212 u8 funcs[4]; 213 #if defined(CONFIG_TEGRA20) 214 u8 ctl_id; 215 u8 pull_id; 216 #endif /* CONFIG_TEGRA20 */ 217 }; 218 219 extern const struct pmux_pingrp_desc *tegra_soc_pingroups; 220 221 #endif /* _TEGRA_PINMUX_H_ */ 222