1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <asm/arch/tegra.h> 12 13 /* The pullup/pulldown state of a pin group */ 14 enum pmux_pull { 15 PMUX_PULL_NORMAL = 0, 16 PMUX_PULL_DOWN, 17 PMUX_PULL_UP, 18 }; 19 20 /* Defines whether a pin group is tristated or in normal operation */ 21 enum pmux_tristate { 22 PMUX_TRI_NORMAL = 0, 23 PMUX_TRI_TRISTATE = 1, 24 }; 25 26 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 27 enum pmux_pin_io { 28 PMUX_PIN_OUTPUT = 0, 29 PMUX_PIN_INPUT = 1, 30 PMUX_PIN_NONE, 31 }; 32 33 enum pmux_pin_lock { 34 PMUX_PIN_LOCK_DEFAULT = 0, 35 PMUX_PIN_LOCK_DISABLE, 36 PMUX_PIN_LOCK_ENABLE, 37 }; 38 39 enum pmux_pin_od { 40 PMUX_PIN_OD_DEFAULT = 0, 41 PMUX_PIN_OD_DISABLE, 42 PMUX_PIN_OD_ENABLE, 43 }; 44 45 enum pmux_pin_ioreset { 46 PMUX_PIN_IO_RESET_DEFAULT = 0, 47 PMUX_PIN_IO_RESET_DISABLE, 48 PMUX_PIN_IO_RESET_ENABLE, 49 }; 50 51 #ifdef TEGRA_PMX_HAS_RCV_SEL 52 enum pmux_pin_rcv_sel { 53 PMUX_PIN_RCV_SEL_DEFAULT = 0, 54 PMUX_PIN_RCV_SEL_NORMAL, 55 PMUX_PIN_RCV_SEL_HIGH, 56 }; 57 #endif /* TEGRA_PMX_HAS_RCV_SEL */ 58 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */ 59 60 /* 61 * This defines the configuration for a pin, including the function assigned, 62 * pull up/down settings and tristate settings. Having set up one of these 63 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 64 * available is pinmux_config_table() to configure a list of pins. 65 */ 66 struct pmux_pingrp_config { 67 u32 pingrp:16; /* pin group PMUX_PINGRP_... */ 68 u32 func:8; /* function to assign PMUX_FUNC_... */ 69 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ 70 u32 tristate:2; /* tristate or normal PMUX_TRI_... */ 71 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 72 u32 io:2; /* input or output PMUX_PIN_... */ 73 u32 lock:2; /* lock enable/disable PMUX_PIN... */ 74 u32 od:2; /* open-drain or push-pull driver */ 75 u32 ioreset:2; /* input/output reset PMUX_PIN... */ 76 #ifdef TEGRA_PMX_HAS_RCV_SEL 77 u32 rcv_sel:2; /* select between High and Normal */ 78 /* VIL/VIH receivers */ 79 #endif 80 #endif 81 }; 82 83 #if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30) 84 /* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ 85 void pinmux_set_tristate_input_clamping(void); 86 #endif 87 88 /* Set the mux function for a pin group */ 89 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 90 91 /* Set the pull up/down feature for a pin group */ 92 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 93 94 /* Set a pin group to tristate */ 95 void pinmux_tristate_enable(enum pmux_pingrp pin); 96 97 /* Set a pin group to normal (non tristate) */ 98 void pinmux_tristate_disable(enum pmux_pingrp pin); 99 100 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC 101 /* Set a pin group as input or output */ 102 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 103 #endif 104 105 /** 106 * Configure a list of pin groups 107 * 108 * @param config List of config items 109 * @param len Number of config items in list 110 */ 111 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, 112 int len); 113 114 #ifdef TEGRA_PMX_HAS_DRVGRPS 115 116 #define PMUX_SLWF_MIN 0 117 #define PMUX_SLWF_MAX 3 118 #define PMUX_SLWF_NONE -1 119 120 #define PMUX_SLWR_MIN 0 121 #define PMUX_SLWR_MAX 3 122 #define PMUX_SLWR_NONE -1 123 124 #define PMUX_DRVUP_MIN 0 125 #define PMUX_DRVUP_MAX 127 126 #define PMUX_DRVUP_NONE -1 127 128 #define PMUX_DRVDN_MIN 0 129 #define PMUX_DRVDN_MAX 127 130 #define PMUX_DRVDN_NONE -1 131 132 /* Defines a pin group cfg's low-power mode select */ 133 enum pmux_lpmd { 134 PMUX_LPMD_X8 = 0, 135 PMUX_LPMD_X4, 136 PMUX_LPMD_X2, 137 PMUX_LPMD_X, 138 PMUX_LPMD_NONE = -1, 139 }; 140 141 /* Defines whether a pin group cfg's schmidt is enabled or not */ 142 enum pmux_schmt { 143 PMUX_SCHMT_DISABLE = 0, 144 PMUX_SCHMT_ENABLE = 1, 145 PMUX_SCHMT_NONE = -1, 146 }; 147 148 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 149 enum pmux_hsm { 150 PMUX_HSM_DISABLE = 0, 151 PMUX_HSM_ENABLE = 1, 152 PMUX_HSM_NONE = -1, 153 }; 154 155 /* 156 * This defines the configuration for a pin group's pad control config 157 */ 158 struct pmux_drvgrp_config { 159 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ 160 u32 slwf:3; /* falling edge slew */ 161 u32 slwr:3; /* rising edge slew */ 162 u32 drvup:8; /* pull-up drive strength */ 163 u32 drvdn:8; /* pull-down drive strength */ 164 u32 lpmd:3; /* low-power mode selection */ 165 u32 schmt:2; /* schmidt enable */ 166 u32 hsm:2; /* high-speed mode enable */ 167 }; 168 169 /** 170 * Set the GP pad configs 171 * 172 * @param config List of config items 173 * @param len Number of config items in list 174 */ 175 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, 176 int len); 177 178 #endif /* TEGRA_PMX_HAS_DRVGRPS */ 179 180 struct pmux_pingrp_desc { 181 u8 funcs[4]; 182 #if defined(CONFIG_TEGRA20) 183 u8 ctl_id; 184 u8 pull_id; 185 #endif /* CONFIG_TEGRA20 */ 186 }; 187 188 extern const struct pmux_pingrp_desc *tegra_soc_pingroups; 189 190 #endif /* _TEGRA_PINMUX_H_ */ 191