1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <linux/types.h> 12 13 #include <asm/arch/tegra.h> 14 15 /* The pullup/pulldown state of a pin group */ 16 enum pmux_pull { 17 PMUX_PULL_NORMAL = 0, 18 PMUX_PULL_DOWN, 19 PMUX_PULL_UP, 20 }; 21 22 /* Defines whether a pin group is tristated or in normal operation */ 23 enum pmux_tristate { 24 PMUX_TRI_NORMAL = 0, 25 PMUX_TRI_TRISTATE = 1, 26 }; 27 28 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 29 enum pmux_pin_io { 30 PMUX_PIN_OUTPUT = 0, 31 PMUX_PIN_INPUT = 1, 32 PMUX_PIN_NONE, 33 }; 34 #endif 35 36 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 37 enum pmux_pin_lock { 38 PMUX_PIN_LOCK_DEFAULT = 0, 39 PMUX_PIN_LOCK_DISABLE, 40 PMUX_PIN_LOCK_ENABLE, 41 }; 42 #endif 43 44 #ifdef TEGRA_PMX_PINS_HAVE_OD 45 enum pmux_pin_od { 46 PMUX_PIN_OD_DEFAULT = 0, 47 PMUX_PIN_OD_DISABLE, 48 PMUX_PIN_OD_ENABLE, 49 }; 50 #endif 51 52 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 53 enum pmux_pin_ioreset { 54 PMUX_PIN_IO_RESET_DEFAULT = 0, 55 PMUX_PIN_IO_RESET_DISABLE, 56 PMUX_PIN_IO_RESET_ENABLE, 57 }; 58 #endif 59 60 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 61 enum pmux_pin_rcv_sel { 62 PMUX_PIN_RCV_SEL_DEFAULT = 0, 63 PMUX_PIN_RCV_SEL_NORMAL, 64 PMUX_PIN_RCV_SEL_HIGH, 65 }; 66 #endif 67 68 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV 69 enum pmux_pin_e_io_hv { 70 PMUX_PIN_E_IO_HV_DEFAULT = 0, 71 PMUX_PIN_E_IO_HV_NORMAL, 72 PMUX_PIN_E_IO_HV_HIGH, 73 }; 74 #endif 75 76 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 77 /* Defines a pin group cfg's low-power mode select */ 78 enum pmux_lpmd { 79 PMUX_LPMD_X8 = 0, 80 PMUX_LPMD_X4, 81 PMUX_LPMD_X2, 82 PMUX_LPMD_X, 83 PMUX_LPMD_NONE = -1, 84 }; 85 #endif 86 87 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) 88 /* Defines whether a pin group cfg's schmidt is enabled or not */ 89 enum pmux_schmt { 90 PMUX_SCHMT_DISABLE = 0, 91 PMUX_SCHMT_ENABLE = 1, 92 PMUX_SCHMT_NONE = -1, 93 }; 94 #endif 95 96 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) 97 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 98 enum pmux_hsm { 99 PMUX_HSM_DISABLE = 0, 100 PMUX_HSM_ENABLE = 1, 101 PMUX_HSM_NONE = -1, 102 }; 103 #endif 104 105 /* 106 * This defines the configuration for a pin, including the function assigned, 107 * pull up/down settings and tristate settings. Having set up one of these 108 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 109 * available is pinmux_config_table() to configure a list of pins. 110 */ 111 struct pmux_pingrp_config { 112 u32 pingrp:16; /* pin group PMUX_PINGRP_... */ 113 u32 func:8; /* function to assign PMUX_FUNC_... */ 114 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ 115 u32 tristate:2; /* tristate or normal PMUX_TRI_... */ 116 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 117 u32 io:2; /* input or output PMUX_PIN_... */ 118 #endif 119 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 120 u32 lock:2; /* lock enable/disable PMUX_PIN... */ 121 #endif 122 #ifdef TEGRA_PMX_PINS_HAVE_OD 123 u32 od:2; /* open-drain or push-pull driver */ 124 #endif 125 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 126 u32 ioreset:2; /* input/output reset PMUX_PIN... */ 127 #endif 128 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 129 u32 rcv_sel:2; /* select between High and Normal */ 130 /* VIL/VIH receivers */ 131 #endif 132 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV 133 u32 e_io_hv:2; /* select 3.3v tolerant receivers */ 134 #endif 135 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT 136 u32 schmt:2; /* schmitt enable */ 137 #endif 138 #ifdef TEGRA_PMX_PINS_HAVE_HSM 139 u32 hsm:2; /* high-speed mode enable */ 140 #endif 141 }; 142 143 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING 144 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ 145 void pinmux_set_tristate_input_clamping(void); 146 void pinmux_clear_tristate_input_clamping(void); 147 #endif 148 149 /* Set the mux function for a pin group */ 150 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 151 152 /* Set the pull up/down feature for a pin group */ 153 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 154 155 /* Set a pin group to tristate */ 156 void pinmux_tristate_enable(enum pmux_pingrp pin); 157 158 /* Set a pin group to normal (non tristate) */ 159 void pinmux_tristate_disable(enum pmux_pingrp pin); 160 161 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 162 /* Set a pin group as input or output */ 163 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 164 #endif 165 166 /** 167 * Configure a list of pin groups 168 * 169 * @param config List of config items 170 * @param len Number of config items in list 171 */ 172 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, 173 int len); 174 175 struct pmux_pingrp_desc { 176 u8 funcs[4]; 177 #if defined(CONFIG_TEGRA20) 178 u8 ctl_id; 179 u8 pull_id; 180 #endif /* CONFIG_TEGRA20 */ 181 }; 182 183 extern const struct pmux_pingrp_desc *tegra_soc_pingroups; 184 185 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS 186 187 #define PMUX_SLWF_MIN 0 188 #define PMUX_SLWF_MAX 3 189 #define PMUX_SLWF_NONE -1 190 191 #define PMUX_SLWR_MIN 0 192 #define PMUX_SLWR_MAX 3 193 #define PMUX_SLWR_NONE -1 194 195 #define PMUX_DRVUP_MIN 0 196 #define PMUX_DRVUP_MAX 127 197 #define PMUX_DRVUP_NONE -1 198 199 #define PMUX_DRVDN_MIN 0 200 #define PMUX_DRVDN_MAX 127 201 #define PMUX_DRVDN_NONE -1 202 203 /* 204 * This defines the configuration for a pin group's pad control config 205 */ 206 struct pmux_drvgrp_config { 207 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ 208 u32 slwf:3; /* falling edge slew */ 209 u32 slwr:3; /* rising edge slew */ 210 u32 drvup:8; /* pull-up drive strength */ 211 u32 drvdn:8; /* pull-down drive strength */ 212 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 213 u32 lpmd:3; /* low-power mode selection */ 214 #endif 215 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT 216 u32 schmt:2; /* schmidt enable */ 217 #endif 218 #ifdef TEGRA_PMX_GRPS_HAVE_HSM 219 u32 hsm:2; /* high-speed mode enable */ 220 #endif 221 }; 222 223 /** 224 * Set the GP pad configs 225 * 226 * @param config List of config items 227 * @param len Number of config items in list 228 */ 229 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, 230 int len); 231 232 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ 233 234 #ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS 235 struct pmux_mipipadctrlgrp_config { 236 u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ 237 u32 func:8; /* function to assign PMUX_FUNC_... */ 238 }; 239 240 void pinmux_config_mipipadctrlgrp_table( 241 const struct pmux_mipipadctrlgrp_config *config, int len); 242 243 struct pmux_mipipadctrlgrp_desc { 244 u8 funcs[2]; 245 }; 246 247 extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; 248 #endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ 249 250 #endif /* _TEGRA_PINMUX_H_ */ 251