1 /* 2 * (C) Copyright 2010-2014 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _TEGRA_PINMUX_H_ 9 #define _TEGRA_PINMUX_H_ 10 11 #include <asm/arch/tegra.h> 12 13 /* The pullup/pulldown state of a pin group */ 14 enum pmux_pull { 15 PMUX_PULL_NORMAL = 0, 16 PMUX_PULL_DOWN, 17 PMUX_PULL_UP, 18 }; 19 20 /* Defines whether a pin group is tristated or in normal operation */ 21 enum pmux_tristate { 22 PMUX_TRI_NORMAL = 0, 23 PMUX_TRI_TRISTATE = 1, 24 }; 25 26 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 27 enum pmux_pin_io { 28 PMUX_PIN_OUTPUT = 0, 29 PMUX_PIN_INPUT = 1, 30 PMUX_PIN_NONE, 31 }; 32 #endif 33 34 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 35 enum pmux_pin_lock { 36 PMUX_PIN_LOCK_DEFAULT = 0, 37 PMUX_PIN_LOCK_DISABLE, 38 PMUX_PIN_LOCK_ENABLE, 39 }; 40 #endif 41 42 #ifdef TEGRA_PMX_PINS_HAVE_OD 43 enum pmux_pin_od { 44 PMUX_PIN_OD_DEFAULT = 0, 45 PMUX_PIN_OD_DISABLE, 46 PMUX_PIN_OD_ENABLE, 47 }; 48 #endif 49 50 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 51 enum pmux_pin_ioreset { 52 PMUX_PIN_IO_RESET_DEFAULT = 0, 53 PMUX_PIN_IO_RESET_DISABLE, 54 PMUX_PIN_IO_RESET_ENABLE, 55 }; 56 #endif 57 58 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 59 enum pmux_pin_rcv_sel { 60 PMUX_PIN_RCV_SEL_DEFAULT = 0, 61 PMUX_PIN_RCV_SEL_NORMAL, 62 PMUX_PIN_RCV_SEL_HIGH, 63 }; 64 #endif 65 66 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV 67 enum pmux_pin_e_io_hv { 68 PMUX_PIN_E_IO_HV_DEFAULT = 0, 69 PMUX_PIN_E_IO_HV_NORMAL, 70 PMUX_PIN_E_IO_HV_HIGH, 71 }; 72 #endif 73 74 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 75 /* Defines a pin group cfg's low-power mode select */ 76 enum pmux_lpmd { 77 PMUX_LPMD_X8 = 0, 78 PMUX_LPMD_X4, 79 PMUX_LPMD_X2, 80 PMUX_LPMD_X, 81 PMUX_LPMD_NONE = -1, 82 }; 83 #endif 84 85 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT) 86 /* Defines whether a pin group cfg's schmidt is enabled or not */ 87 enum pmux_schmt { 88 PMUX_SCHMT_DISABLE = 0, 89 PMUX_SCHMT_ENABLE = 1, 90 PMUX_SCHMT_NONE = -1, 91 }; 92 #endif 93 94 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM) 95 /* Defines whether a pin group cfg's high-speed mode is enabled or not */ 96 enum pmux_hsm { 97 PMUX_HSM_DISABLE = 0, 98 PMUX_HSM_ENABLE = 1, 99 PMUX_HSM_NONE = -1, 100 }; 101 #endif 102 103 /* 104 * This defines the configuration for a pin, including the function assigned, 105 * pull up/down settings and tristate settings. Having set up one of these 106 * you can call pinmux_config_pingroup() to configure a pin in one step. Also 107 * available is pinmux_config_table() to configure a list of pins. 108 */ 109 struct pmux_pingrp_config { 110 u32 pingrp:16; /* pin group PMUX_PINGRP_... */ 111 u32 func:8; /* function to assign PMUX_FUNC_... */ 112 u32 pull:2; /* pull up/down/normal PMUX_PULL_...*/ 113 u32 tristate:2; /* tristate or normal PMUX_TRI_... */ 114 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 115 u32 io:2; /* input or output PMUX_PIN_... */ 116 #endif 117 #ifdef TEGRA_PMX_PINS_HAVE_LOCK 118 u32 lock:2; /* lock enable/disable PMUX_PIN... */ 119 #endif 120 #ifdef TEGRA_PMX_PINS_HAVE_OD 121 u32 od:2; /* open-drain or push-pull driver */ 122 #endif 123 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET 124 u32 ioreset:2; /* input/output reset PMUX_PIN... */ 125 #endif 126 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL 127 u32 rcv_sel:2; /* select between High and Normal */ 128 /* VIL/VIH receivers */ 129 #endif 130 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV 131 u32 e_io_hv:2; /* select 3.3v tolerant receivers */ 132 #endif 133 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT 134 u32 schmt:2; /* schmitt enable */ 135 #endif 136 #ifdef TEGRA_PMX_PINS_HAVE_HSM 137 u32 hsm:2; /* high-speed mode enable */ 138 #endif 139 }; 140 141 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING 142 /* Set/clear the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */ 143 void pinmux_set_tristate_input_clamping(void); 144 void pinmux_clear_tristate_input_clamping(void); 145 #endif 146 147 /* Set the mux function for a pin group */ 148 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func); 149 150 /* Set the pull up/down feature for a pin group */ 151 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd); 152 153 /* Set a pin group to tristate */ 154 void pinmux_tristate_enable(enum pmux_pingrp pin); 155 156 /* Set a pin group to normal (non tristate) */ 157 void pinmux_tristate_disable(enum pmux_pingrp pin); 158 159 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT 160 /* Set a pin group as input or output */ 161 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io); 162 #endif 163 164 /** 165 * Configure a list of pin groups 166 * 167 * @param config List of config items 168 * @param len Number of config items in list 169 */ 170 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config, 171 int len); 172 173 struct pmux_pingrp_desc { 174 u8 funcs[4]; 175 #if defined(CONFIG_TEGRA20) 176 u8 ctl_id; 177 u8 pull_id; 178 #endif /* CONFIG_TEGRA20 */ 179 }; 180 181 extern const struct pmux_pingrp_desc *tegra_soc_pingroups; 182 183 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS 184 185 #define PMUX_SLWF_MIN 0 186 #define PMUX_SLWF_MAX 3 187 #define PMUX_SLWF_NONE -1 188 189 #define PMUX_SLWR_MIN 0 190 #define PMUX_SLWR_MAX 3 191 #define PMUX_SLWR_NONE -1 192 193 #define PMUX_DRVUP_MIN 0 194 #define PMUX_DRVUP_MAX 127 195 #define PMUX_DRVUP_NONE -1 196 197 #define PMUX_DRVDN_MIN 0 198 #define PMUX_DRVDN_MAX 127 199 #define PMUX_DRVDN_NONE -1 200 201 /* 202 * This defines the configuration for a pin group's pad control config 203 */ 204 struct pmux_drvgrp_config { 205 u32 drvgrp:16; /* pin group PMUX_DRVGRP_x */ 206 u32 slwf:3; /* falling edge slew */ 207 u32 slwr:3; /* rising edge slew */ 208 u32 drvup:8; /* pull-up drive strength */ 209 u32 drvdn:8; /* pull-down drive strength */ 210 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD 211 u32 lpmd:3; /* low-power mode selection */ 212 #endif 213 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT 214 u32 schmt:2; /* schmidt enable */ 215 #endif 216 #ifdef TEGRA_PMX_GRPS_HAVE_HSM 217 u32 hsm:2; /* high-speed mode enable */ 218 #endif 219 }; 220 221 /** 222 * Set the GP pad configs 223 * 224 * @param config List of config items 225 * @param len Number of config items in list 226 */ 227 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config, 228 int len); 229 230 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */ 231 232 #ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS 233 struct pmux_mipipadctrlgrp_config { 234 u32 grp:16; /* pin group PMUX_MIPIPADCTRLGRP_x */ 235 u32 func:8; /* function to assign PMUX_FUNC_... */ 236 }; 237 238 void pinmux_config_mipipadctrlgrp_table( 239 const struct pmux_mipipadctrlgrp_config *config, int len); 240 241 struct pmux_mipipadctrlgrp_desc { 242 u8 funcs[2]; 243 }; 244 245 extern const struct pmux_mipipadctrlgrp_desc *tegra_soc_mipipadctrl_groups; 246 #endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */ 247 248 #endif /* _TEGRA_PINMUX_H_ */ 249