1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2dc89ad14STom Warren /* 37aaa5a60STom Warren * (C) Copyright 2010-2015 4dc89ad14STom Warren * NVIDIA Corporation <www.nvidia.com> 5dc89ad14STom Warren */ 6dc89ad14STom Warren 7dc89ad14STom Warren #ifndef _TEGRA_GP_PADCTRL_H_ 8dc89ad14STom Warren #define _TEGRA_GP_PADCTRL_H_ 9dc89ad14STom Warren 10dc89ad14STom Warren #define GP_HIDREV 0x804 11dc89ad14STom Warren 12dc89ad14STom Warren /* bit fields definitions for APB_MISC_GP_HIDREV register */ 13dc89ad14STom Warren #define HIDREV_CHIPID_SHIFT 8 14dc89ad14STom Warren #define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT) 15dc89ad14STom Warren #define HIDREV_MAJORPREV_SHIFT 4 16dc89ad14STom Warren #define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT) 17dc89ad14STom Warren 18dc89ad14STom Warren /* CHIPID field returned from APB_MISC_GP_HIDREV register */ 19dc89ad14STom Warren #define CHIPID_TEGRA20 0x20 20dc89ad14STom Warren #define CHIPID_TEGRA30 0x30 212fc65e28STom Warren #define CHIPID_TEGRA114 0x35 22999c6bafSTom Warren #define CHIPID_TEGRA124 0x40 237aaa5a60STom Warren #define CHIPID_TEGRA210 0x21 24dc89ad14STom Warren 25dc89ad14STom Warren #endif /* _TEGRA_GP_PADCTRL_H_ */ 26