1 /* 2 * (C) Copyright 2010 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ASM_ARCH_TEGRA_DC_H 9 #define __ASM_ARCH_TEGRA_DC_H 10 11 /* Register definitions for the Tegra display controller */ 12 13 /* CMD register 0x000 ~ 0x43 */ 14 struct dc_cmd_reg { 15 /* Address 0x000 ~ 0x002 */ 16 uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ 17 uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ 18 uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ 19 20 uint reserved0[5]; /* reserved_0[5] */ 21 22 /* Address 0x008 ~ 0x00a */ 23 uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ 24 uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ 25 uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ 26 27 uint reserved1[5]; /* reserved_1[5] */ 28 29 /* Address 0x010 ~ 0x012 */ 30 uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ 31 uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ 32 uint win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ 33 34 uint reserved2[5]; /* reserved_2[5] */ 35 36 /* Address 0x018 ~ 0x01a */ 37 uint win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ 38 uint win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ 39 uint win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ 40 41 uint reserved3[13]; /* reserved_3[13] */ 42 43 /* Address 0x028 */ 44 uint cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ 45 46 uint reserved4[7]; /* reserved_4[7] */ 47 48 /* Address 0x030 ~ 0x033 */ 49 uint ctxsw; /* _CMD_CTXSW_0 */ 50 uint disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ 51 uint disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ 52 uint sig_raise; /* _CMD_SIGNAL_RAISE_0 */ 53 54 uint reserved5[2]; /* reserved_0[2] */ 55 56 /* Address 0x036 ~ 0x03e */ 57 uint disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ 58 uint int_stat; /* _CMD_INT_STATUS_0 */ 59 uint int_mask; /* _CMD_INT_MASK_0 */ 60 uint int_enb; /* _CMD_INT_ENABLE_0 */ 61 uint int_type; /* _CMD_INT_TYPE_0 */ 62 uint int_polarity; /* _CMD_INT_POLARITY_0 */ 63 uint sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ 64 uint sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ 65 uint sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ 66 67 uint reserved6; /* reserved_6 */ 68 69 /* Address 0x040 ~ 0x043 */ 70 uint state_access; /* _CMD_STATE_ACCESS_0 */ 71 uint state_ctrl; /* _CMD_STATE_CONTROL_0 */ 72 uint disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ 73 uint reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ 74 }; 75 76 enum { 77 PIN_REG_COUNT = 4, 78 PIN_OUTPUT_SEL_COUNT = 7, 79 }; 80 81 /* COM register 0x300 ~ 0x329 */ 82 struct dc_com_reg { 83 /* Address 0x300 ~ 0x301 */ 84 uint crc_ctrl; /* _COM_CRC_CONTROL_0 */ 85 uint crc_checksum; /* _COM_CRC_CHECKSUM_0 */ 86 87 /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ 88 uint pin_output_enb[PIN_REG_COUNT]; 89 90 /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ 91 uint pin_output_polarity[PIN_REG_COUNT]; 92 93 /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ 94 uint pin_output_data[PIN_REG_COUNT]; 95 96 /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ 97 uint pin_input_enb[PIN_REG_COUNT]; 98 99 /* Address 0x312 ~ 0x313 */ 100 uint pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ 101 uint pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ 102 103 /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ 104 uint pin_output_sel[PIN_OUTPUT_SEL_COUNT]; 105 106 /* Address 0x31b ~ 0x329 */ 107 uint pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ 108 uint pm0_ctrl; /* _COM_PM0_CONTROL_0 */ 109 uint pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ 110 uint pm1_ctrl; /* _COM_PM1_CONTROL_0 */ 111 uint pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ 112 uint spi_ctrl; /* _COM_SPI_CONTROL_0 */ 113 uint spi_start_byte; /* _COM_SPI_START_BYTE_0 */ 114 uint hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ 115 uint hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ 116 uint hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ 117 uint scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ 118 uint scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ 119 uint gpio_ctrl; /* _COM_GPIO_CTRL_0 */ 120 uint gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ 121 uint crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ 122 }; 123 124 enum dc_disp_h_pulse_pos { 125 H_PULSE0_POSITION_A, 126 H_PULSE0_POSITION_B, 127 H_PULSE0_POSITION_C, 128 H_PULSE0_POSITION_D, 129 H_PULSE0_POSITION_COUNT, 130 }; 131 132 struct _disp_h_pulse { 133 /* _DISP_H_PULSE0/1/2_CONTROL_0 */ 134 uint h_pulse_ctrl; 135 /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ 136 uint h_pulse_pos[H_PULSE0_POSITION_COUNT]; 137 }; 138 139 enum dc_disp_v_pulse_pos { 140 V_PULSE0_POSITION_A, 141 V_PULSE0_POSITION_B, 142 V_PULSE0_POSITION_C, 143 V_PULSE0_POSITION_COUNT, 144 }; 145 146 struct _disp_v_pulse0 { 147 /* _DISP_H_PULSE0/1_CONTROL_0 */ 148 uint v_pulse_ctrl; 149 /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ 150 uint v_pulse_pos[V_PULSE0_POSITION_COUNT]; 151 }; 152 153 struct _disp_v_pulse2 { 154 /* _DISP_H_PULSE2/3_CONTROL_0 */ 155 uint v_pulse_ctrl; 156 /* _DISP_H_PULSE2/3_POSITION_A_0 */ 157 uint v_pulse_pos_a; 158 }; 159 160 enum dc_disp_h_pulse_reg { 161 H_PULSE0, 162 H_PULSE1, 163 H_PULSE2, 164 H_PULSE_COUNT, 165 }; 166 167 enum dc_disp_pp_select { 168 PP_SELECT_A, 169 PP_SELECT_B, 170 PP_SELECT_C, 171 PP_SELECT_D, 172 PP_SELECT_COUNT, 173 }; 174 175 /* DISP register 0x400 ~ 0x4c1 */ 176 struct dc_disp_reg { 177 /* Address 0x400 ~ 0x40a */ 178 uint disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ 179 uint disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ 180 uint disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ 181 uint mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ 182 uint mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ 183 uint disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ 184 uint ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ 185 uint sync_width; /* _DISP_SYNC_WIDTH_0 */ 186 uint back_porch; /* _DISP_BACK_PORCH_0 */ 187 uint disp_active; /* _DISP_DISP_ACTIVE_0 */ 188 uint front_porch; /* _DISP_FRONT_PORCH_0 */ 189 190 /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ 191 struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; 192 193 /* Address 0x41a ~ 0x421 */ 194 struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ 195 struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ 196 197 /* Address 0x422 ~ 0x425 */ 198 struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ 199 struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ 200 201 /* Address 0x426 ~ 0x429 */ 202 uint m0_ctrl; /* _DISP_M0_CONTROL_0 */ 203 uint m1_ctrl; /* _DISP_M1_CONTROL_0 */ 204 uint di_ctrl; /* _DISP_DI_CONTROL_0 */ 205 uint pp_ctrl; /* _DISP_PP_CONTROL_0 */ 206 207 /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ 208 uint pp_select[PP_SELECT_COUNT]; 209 210 /* Address 0x42e ~ 0x435 */ 211 uint disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ 212 uint disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ 213 uint disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ 214 uint shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ 215 uint data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ 216 uint serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ 217 uint lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ 218 uint border_color; /* _DISP_BORDER_COLOR_0 */ 219 220 /* Address 0x436 ~ 0x439 */ 221 uint color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ 222 uint color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ 223 uint color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ 224 uint color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ 225 226 uint reserved0[2]; /* reserved_0[2] */ 227 228 /* Address 0x43c ~ 0x442 */ 229 uint cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ 230 uint cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ 231 uint cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ 232 uint cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ 233 uint cursor_pos; /* _DISP_CURSOR_POSITION_0 */ 234 uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ 235 uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ 236 237 /* Address 0x443 ~ 0x446 */ 238 uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ 239 uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ 240 uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ 241 uint spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ 242 243 uint reserved1[0x39]; /* reserved1[0x39], */ 244 245 /* Address 0x480 ~ 0x484 */ 246 uint dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ 247 uint mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ 248 uint mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ 249 uint mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ 250 uint mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ 251 252 uint reserved2[0x3b]; /* reserved2[0x3b] */ 253 254 /* Address 0x4c0 ~ 0x4c1 */ 255 uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ 256 uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ 257 258 u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ 259 260 /* Address 0x4e4 */ 261 u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ 262 }; 263 264 enum dc_winc_filter_p { 265 WINC_FILTER_COUNT = 0x10, 266 }; 267 268 /* Window A/B/C register 0x500 ~ 0x628 */ 269 struct dc_winc_reg { 270 271 /* Address 0x500 */ 272 uint color_palette; /* _WINC_COLOR_PALETTE_0 */ 273 274 uint reserved0[0xff]; /* reserved_0[0xff] */ 275 276 /* Address 0x600 */ 277 uint palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ 278 279 /* _WINC_H_FILTER_P00~0F_0 */ 280 /* Address 0x601 ~ 0x610 */ 281 uint h_filter_p[WINC_FILTER_COUNT]; 282 283 /* Address 0x611 ~ 0x618 */ 284 uint csc_yof; /* _WINC_CSC_YOF_0 */ 285 uint csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ 286 uint csc_kur; /* _WINC_CSC_KUR_0 */ 287 uint csc_kvr; /* _WINC_CSC_KVR_0 */ 288 uint csc_kug; /* _WINC_CSC_KUG_0 */ 289 uint csc_kvg; /* _WINC_CSC_KVG_0 */ 290 uint csc_kub; /* _WINC_CSC_KUB_0 */ 291 uint csc_kvb; /* _WINC_CSC_KVB_0 */ 292 293 /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ 294 uint v_filter_p[WINC_FILTER_COUNT]; 295 }; 296 297 /* WIN A/B/C Register 0x700 ~ 0x719*/ 298 struct dc_win_reg { 299 /* Address 0x700 ~ 0x719 */ 300 uint win_opt; /* _WIN_WIN_OPTIONS_0 */ 301 uint byte_swap; /* _WIN_BYTE_SWAP_0 */ 302 uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ 303 uint color_depth; /* _WIN_COLOR_DEPTH_0 */ 304 uint pos; /* _WIN_POSITION_0 */ 305 uint size; /* _WIN_SIZE_0 */ 306 uint prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ 307 uint h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ 308 uint v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ 309 uint dda_increment; /* _WIN_DDA_INCREMENT_0 */ 310 uint line_stride; /* _WIN_LINE_STRIDE_0 */ 311 uint buf_stride; /* _WIN_BUF_STRIDE_0 */ 312 uint uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ 313 uint buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ 314 uint dv_ctrl; /* _WIN_DV_CONTROL_0 */ 315 uint blend_nokey; /* _WIN_BLEND_NOKEY_0 */ 316 uint blend_1win; /* _WIN_BLEND_1WIN_0 */ 317 uint blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ 318 uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ 319 uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ 320 uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ 321 uint global_alpha; /* _WIN_GLOBAL_ALPHA */ 322 uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ 323 uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ 324 uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ 325 uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ 326 }; 327 328 /* WINBUF A/B/C Register 0x800 ~ 0x80d */ 329 struct dc_winbuf_reg { 330 /* Address 0x800 ~ 0x80d */ 331 uint start_addr; /* _WINBUF_START_ADDR_0 */ 332 uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ 333 uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */ 334 uint start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ 335 uint start_addr_v; /* _WINBUF_START_ADDR_V_0 */ 336 uint start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ 337 uint addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ 338 uint addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ 339 uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ 340 uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ 341 uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ 342 uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ 343 uint rsvd_80c; 344 uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ 345 }; 346 347 /* Display Controller (DC_) regs */ 348 struct dc_ctlr { 349 struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ 350 uint reserved0[0x2bc]; 351 352 struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ 353 uint reserved1[0xd6]; 354 355 struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ 356 uint reserved2[0x1b]; 357 358 struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ 359 uint reserved3[0xd7]; 360 361 struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ 362 uint reserved4[0xe6]; 363 364 struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ 365 }; 366 367 /* DC_CMD_DISPLAY_COMMAND 0x032 */ 368 #define CTRL_MODE_SHIFT 5 369 #define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) 370 enum { 371 CTRL_MODE_STOP, 372 CTRL_MODE_C_DISPLAY, 373 CTRL_MODE_NC_DISPLAY, 374 }; 375 376 /* _WIN_COLOR_DEPTH_0 */ 377 enum win_color_depth_id { 378 COLOR_DEPTH_P1, 379 COLOR_DEPTH_P2, 380 COLOR_DEPTH_P4, 381 COLOR_DEPTH_P8, 382 COLOR_DEPTH_B4G4R4A4, 383 COLOR_DEPTH_B5G5R5A, 384 COLOR_DEPTH_B5G6R5, 385 COLOR_DEPTH_AB5G5R5, 386 COLOR_DEPTH_B8G8R8A8 = 12, 387 COLOR_DEPTH_R8G8B8A8, 388 COLOR_DEPTH_B6x2G6x2R6x2A8, 389 COLOR_DEPTH_R6x2G6x2B6x2A8, 390 COLOR_DEPTH_YCbCr422, 391 COLOR_DEPTH_YUV422, 392 COLOR_DEPTH_YCbCr420P, 393 COLOR_DEPTH_YUV420P, 394 COLOR_DEPTH_YCbCr422P, 395 COLOR_DEPTH_YUV422P, 396 COLOR_DEPTH_YCbCr422R, 397 COLOR_DEPTH_YUV422R, 398 COLOR_DEPTH_YCbCr422RA, 399 COLOR_DEPTH_YUV422RA, 400 }; 401 402 /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ 403 #define PW0_ENABLE BIT(0) 404 #define PW1_ENABLE BIT(2) 405 #define PW2_ENABLE BIT(4) 406 #define PW3_ENABLE BIT(6) 407 #define PW4_ENABLE BIT(8) 408 #define PM0_ENABLE BIT(16) 409 #define PM1_ENABLE BIT(18) 410 #define SPI_ENABLE BIT(24) 411 #define HSPI_ENABLE BIT(25) 412 413 /* DC_CMD_STATE_ACCESS 0x040 */ 414 #define READ_MUX_ASSEMBLY (0 << 0) 415 #define READ_MUX_ACTIVE (1 << 0) 416 #define WRITE_MUX_ASSEMBLY (0 << 2) 417 #define WRITE_MUX_ACTIVE (1 << 2) 418 419 /* DC_CMD_STATE_CONTROL 0x041 */ 420 #define GENERAL_ACT_REQ BIT(0) 421 #define WIN_A_ACT_REQ BIT(1) 422 #define WIN_B_ACT_REQ BIT(2) 423 #define WIN_C_ACT_REQ BIT(3) 424 #define WIN_D_ACT_REQ BIT(4) 425 #define WIN_H_ACT_REQ BIT(5) 426 #define CURSOR_ACT_REQ BIT(7) 427 #define GENERAL_UPDATE BIT(8) 428 #define WIN_A_UPDATE BIT(9) 429 #define WIN_B_UPDATE BIT(10) 430 #define WIN_C_UPDATE BIT(11) 431 #define WIN_D_UPDATE BIT(12) 432 #define WIN_H_UPDATE BIT(13) 433 #define CURSOR_UPDATE BIT(15) 434 #define NC_HOST_TRIG BIT(24) 435 436 /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ 437 #define WINDOW_A_SELECT BIT(4) 438 #define WINDOW_B_SELECT BIT(5) 439 #define WINDOW_C_SELECT BIT(6) 440 #define WINDOW_D_SELECT BIT(7) 441 #define WINDOW_H_SELECT BIT(8) 442 443 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ 444 #define CURSOR_ENABLE BIT(16) 445 #define SOR_ENABLE BIT(25) 446 #define TVO_ENABLE BIT(28) 447 #define DSI_ENABLE BIT(29) 448 #define HDMI_ENABLE BIT(30) 449 450 /* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ 451 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 452 453 /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ 454 #define SHIFT_CLK_DIVIDER_SHIFT 0 455 #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) 456 #define PIXEL_CLK_DIVIDER_SHIFT 8 457 #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) 458 enum { 459 PIXEL_CLK_DIVIDER_PCD1, 460 PIXEL_CLK_DIVIDER_PCD1H, 461 PIXEL_CLK_DIVIDER_PCD2, 462 PIXEL_CLK_DIVIDER_PCD3, 463 PIXEL_CLK_DIVIDER_PCD4, 464 PIXEL_CLK_DIVIDER_PCD6, 465 PIXEL_CLK_DIVIDER_PCD8, 466 PIXEL_CLK_DIVIDER_PCD9, 467 PIXEL_CLK_DIVIDER_PCD12, 468 PIXEL_CLK_DIVIDER_PCD16, 469 PIXEL_CLK_DIVIDER_PCD18, 470 PIXEL_CLK_DIVIDER_PCD24, 471 PIXEL_CLK_DIVIDER_PCD13, 472 }; 473 474 /* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ 475 #define DATA_FORMAT_SHIFT 0 476 #define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) 477 enum { 478 DATA_FORMAT_DF1P1C, 479 DATA_FORMAT_DF1P2C24B, 480 DATA_FORMAT_DF1P2C18B, 481 DATA_FORMAT_DF1P2C16B, 482 DATA_FORMAT_DF2S, 483 DATA_FORMAT_DF3S, 484 DATA_FORMAT_DFSPI, 485 DATA_FORMAT_DF1P3C24B, 486 DATA_FORMAT_DF1P3C18B, 487 }; 488 #define DATA_ALIGNMENT_SHIFT 8 489 enum { 490 DATA_ALIGNMENT_MSB, 491 DATA_ALIGNMENT_LSB, 492 }; 493 #define DATA_ORDER_SHIFT 9 494 enum { 495 DATA_ORDER_RED_BLUE, 496 DATA_ORDER_BLUE_RED, 497 }; 498 499 /* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ 500 #define DE_SELECT_SHIFT 0 501 #define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) 502 #define DE_SELECT_ACTIVE_BLANK 0x0 503 #define DE_SELECT_ACTIVE 0x1 504 #define DE_SELECT_ACTIVE_IS 0x2 505 #define DE_CONTROL_SHIFT 2 506 #define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) 507 enum { 508 DE_CONTROL_ONECLK, 509 DE_CONTROL_NORMAL, 510 DE_CONTROL_EARLY_EXT, 511 DE_CONTROL_EARLY, 512 DE_CONTROL_ACTIVE_BLANK, 513 }; 514 515 /* DC_WIN_WIN_OPTIONS 0x700 */ 516 #define H_DIRECTION BIT(0) 517 enum { 518 H_DIRECTION_INCREMENT, 519 H_DIRECTION_DECREMENT, 520 }; 521 #define V_DIRECTION BIT(2) 522 enum { 523 V_DIRECTION_INCREMENT, 524 V_DIRECTION_DECREMENT, 525 }; 526 #define COLOR_EXPAND BIT(6) 527 #define CP_ENABLE BIT(16) 528 #define DV_ENABLE BIT(20) 529 #define WIN_ENABLE BIT(30) 530 531 /* DC_WIN_BYTE_SWAP 0x701 */ 532 #define BYTE_SWAP_SHIFT 0 533 #define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) 534 enum { 535 BYTE_SWAP_NOSWAP, 536 BYTE_SWAP_SWAP2, 537 BYTE_SWAP_SWAP4, 538 BYTE_SWAP_SWAP4HW 539 }; 540 541 /* DC_WIN_POSITION 0x704 */ 542 #define H_POSITION_SHIFT 0 543 #define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) 544 #define V_POSITION_SHIFT 16 545 #define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) 546 547 /* DC_WIN_SIZE 0x705 */ 548 #define H_SIZE_SHIFT 0 549 #define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) 550 #define V_SIZE_SHIFT 16 551 #define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) 552 553 /* DC_WIN_PRESCALED_SIZE 0x706 */ 554 #define H_PRESCALED_SIZE_SHIFT 0 555 #define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) 556 #define V_PRESCALED_SIZE_SHIFT 16 557 #define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) 558 559 /* DC_WIN_DDA_INCREMENT 0x709 */ 560 #define H_DDA_INC_SHIFT 0 561 #define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) 562 #define V_DDA_INC_SHIFT 16 563 #define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) 564 565 #define DC_POLL_TIMEOUT_MS 50 566 #define DC_N_WINDOWS 5 567 #define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5) 568 569 struct display_timing; 570 571 int display_init(void *lcdbase, int fb_bits_per_pixel, 572 struct display_timing *timing); 573 574 #endif /* __ASM_ARCH_TEGRA_DC_H */ 575