1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* Tegra clock control functions */ 8 9 #ifndef _TEGRA_CLOCK_H_ 10 #define _TEGRA_CLOCK_H_ 11 12 /* Set of oscillator frequencies supported in the internal API. */ 13 enum clock_osc_freq { 14 /* All in MHz, so 13_0 is 13.0MHz */ 15 CLOCK_OSC_FREQ_13_0, 16 CLOCK_OSC_FREQ_19_2, 17 CLOCK_OSC_FREQ_12_0, 18 CLOCK_OSC_FREQ_26_0, 19 CLOCK_OSC_FREQ_38_4, 20 CLOCK_OSC_FREQ_48_0, 21 22 CLOCK_OSC_FREQ_COUNT, 23 }; 24 25 /* 26 * Note that no Tegra clock register actually uses all of bits 31:28 as 27 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 28 * those cases, nothing is stored in the bits about the mux field, so it's 29 * safe to pretend that the mux field extends all the way to the end of the 30 * register. As such, the U-Boot clock driver is currently a bit lazy, and 31 * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps 32 * them all together and pretends they're all 31:28. 33 */ 34 enum { 35 MASK_BITS_31_30, 36 MASK_BITS_31_29, 37 MASK_BITS_31_28, 38 }; 39 40 #include <asm/arch/clock-tables.h> 41 /* PLL stabilization delay in usec */ 42 #define CLOCK_PLL_STABLE_DELAY_US 300 43 44 /* return the current oscillator clock frequency */ 45 enum clock_osc_freq clock_get_osc_freq(void); 46 47 /* return the clk_m frequency */ 48 unsigned int clk_m_get_rate(unsigned int parent_rate); 49 50 /** 51 * Start PLL using the provided configuration parameters. 52 * 53 * @param id clock id 54 * @param divm input divider 55 * @param divn feedback divider 56 * @param divp post divider 2^n 57 * @param cpcon charge pump setup control 58 * @param lfcon loop filter setup control 59 * 60 * @returns monotonic time in us that the PLL will be stable 61 */ 62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 63 u32 divp, u32 cpcon, u32 lfcon); 64 65 /** 66 * Set PLL output frequency 67 * 68 * @param clkid clock id 69 * @param pllout pll output id 70 * @param rate desired output rate 71 * 72 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 73 */ 74 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 75 unsigned rate); 76 77 /** 78 * Read low-level parameters of a PLL. 79 * 80 * @param id clock id to read (note: USB is not supported) 81 * @param divm returns input divider 82 * @param divn returns feedback divider 83 * @param divp returns post divider 2^n 84 * @param cpcon returns charge pump setup control 85 * @param lfcon returns loop filter setup control 86 * 87 * @returns 0 if ok, -1 on error (invalid clock id) 88 */ 89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 90 u32 *divp, u32 *cpcon, u32 *lfcon); 91 92 /* 93 * Enable a clock 94 * 95 * @param id clock id 96 */ 97 void clock_enable(enum periph_id clkid); 98 99 /* 100 * Disable a clock 101 * 102 * @param id clock id 103 */ 104 void clock_disable(enum periph_id clkid); 105 106 /* 107 * Set whether a clock is enabled or disabled. 108 * 109 * @param id clock id 110 * @param enable 1 to enable, 0 to disable 111 */ 112 void clock_set_enable(enum periph_id clkid, int enable); 113 114 /** 115 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 116 * it out of reset and waits for th delay again. 117 * 118 * @param periph_id peripheral to reset 119 * @param us_delay time to delay in microseconds 120 */ 121 void reset_periph(enum periph_id periph_id, int us_delay); 122 123 /** 124 * Put a peripheral into or out of reset. 125 * 126 * @param periph_id peripheral to reset 127 * @param enable 1 to put into reset, 0 to take out of reset 128 */ 129 void reset_set_enable(enum periph_id periph_id, int enable); 130 131 132 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 133 enum crc_reset_id { 134 /* Things we can hold in reset for each CPU */ 135 crc_rst_cpu = 1, 136 crc_rst_de = 1 << 4, /* What is de? */ 137 crc_rst_watchdog = 1 << 8, 138 crc_rst_debug = 1 << 12, 139 }; 140 141 /** 142 * Put parts of the CPU complex into or out of reset.\ 143 * 144 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 145 * @param which which parts of the complex to affect (OR of crc_reset_id) 146 * @param reset 1 to assert reset, 0 to de-assert 147 */ 148 void reset_cmplx_set_enable(int cpu, int which, int reset); 149 150 /** 151 * Set the source for a peripheral clock. This plus the divisor sets the 152 * clock rate. You need to look up the datasheet to see the meaning of the 153 * source parameter as it changes for each peripheral. 154 * 155 * Warning: This function is only for use pre-relocation. Please use 156 * clock_start_periph_pll() instead. 157 * 158 * @param periph_id peripheral to adjust 159 * @param source source clock (0, 1, 2 or 3) 160 */ 161 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 162 163 /** 164 * This function is similar to clock_ll_set_source() except that it can be 165 * used for clocks with more than 2 mux bits. 166 * 167 * @param periph_id peripheral to adjust 168 * @param mux_bits number of mux bits for the clock 169 * @param source source clock (0-15 depending on mux_bits) 170 */ 171 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 172 unsigned source); 173 174 /** 175 * Set the source and divisor for a peripheral clock. This sets the 176 * clock rate. You need to look up the datasheet to see the meaning of the 177 * source parameter as it changes for each peripheral. 178 * 179 * Warning: This function is only for use pre-relocation. Please use 180 * clock_start_periph_pll() instead. 181 * 182 * @param periph_id peripheral to adjust 183 * @param source source clock (0, 1, 2 or 3) 184 * @param divisor divisor value to use 185 */ 186 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 187 unsigned divisor); 188 189 /** 190 * Returns the current parent clock ID of a given peripheral. This can be 191 * useful in order to call clock_*_periph_*() from generic code that has no 192 * specific knowledge of system-level clock tree structure. 193 * 194 * @param periph_id peripheral to query 195 * @return clock ID of the peripheral's current parent clock 196 */ 197 enum clock_id clock_get_periph_parent(enum periph_id periph_id); 198 199 /** 200 * Start a peripheral PLL clock at the given rate. This also resets the 201 * peripheral. 202 * 203 * @param periph_id peripheral to start 204 * @param parent PLL id of required parent clock 205 * @param rate Required clock rate in Hz 206 * @return rate selected in Hz, or -1U if something went wrong 207 */ 208 unsigned clock_start_periph_pll(enum periph_id periph_id, 209 enum clock_id parent, unsigned rate); 210 211 /** 212 * Returns the rate of a peripheral clock in Hz. Since the caller almost 213 * certainly knows the parent clock (having just set it) we require that 214 * this be passed in so we don't need to work it out. 215 * 216 * @param periph_id peripheral to start 217 * @param parent PLL id of parent clock (used to calculate rate, you 218 * must know this!) 219 * @return clock rate of peripheral in Hz 220 */ 221 unsigned long clock_get_periph_rate(enum periph_id periph_id, 222 enum clock_id parent); 223 224 /** 225 * Adjust peripheral PLL clock to the given rate. This does not reset the 226 * peripheral. If a second stage divisor is not available, pass NULL for 227 * extra_div. If it is available, then this parameter will return the 228 * divisor selected (which will be a power of 2 from 1 to 256). 229 * 230 * @param periph_id peripheral to start 231 * @param parent PLL id of required parent clock 232 * @param rate Required clock rate in Hz 233 * @param extra_div value for the second-stage divisor (NULL if one is 234 not available) 235 * @return rate selected in Hz, or -1U if something went wrong 236 */ 237 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 238 enum clock_id parent, unsigned rate, int *extra_div); 239 240 /** 241 * Returns the clock rate of a specified clock, in Hz. 242 * 243 * @param parent PLL id of clock to check 244 * @return rate of clock in Hz 245 */ 246 unsigned clock_get_rate(enum clock_id clkid); 247 248 /** 249 * Start up a UART using low-level calls 250 * 251 * Prior to relocation clock_start_periph_pll() cannot be called. This 252 * function provides a way to set up a UART using low-level calls which 253 * do not require BSS. 254 * 255 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 256 */ 257 void clock_ll_start_uart(enum periph_id periph_id); 258 259 /** 260 * Decode a peripheral ID from a device tree node. 261 * 262 * This works by looking up the peripheral's 'clocks' node and reading out 263 * the second cell, which is the clock number / peripheral ID. 264 * 265 * @param blob FDT blob to use 266 * @param node Node to look at 267 * @return peripheral ID, or PERIPH_ID_NONE if none 268 */ 269 enum periph_id clock_decode_periph_id(const void *blob, int node); 270 271 /** 272 * Checks if the oscillator bypass is enabled (XOBP bit) 273 * 274 * @return 1 if bypass is enabled, 0 if not 275 */ 276 int clock_get_osc_bypass(void); 277 278 /* 279 * Checks that clocks are valid and prints a warning if not 280 * 281 * @return 0 if ok, -1 on error 282 */ 283 int clock_verify(void); 284 285 /* Initialize the clocks */ 286 void clock_init(void); 287 288 /* Initialize the PLLs */ 289 void clock_early_init(void); 290 291 /* Returns a pointer to the clock source register for a peripheral */ 292 u32 *get_periph_source_reg(enum periph_id periph_id); 293 294 /* Returns a pointer to the given 'simple' PLL */ 295 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); 296 297 /* 298 * Given a peripheral ID, determine where the mux bits are in the peripheral 299 * clock's register, the number of divider bits the clock has, and the SoC- 300 * specific clock type. 301 * 302 * This is an internal API between the core Tegra clock code and the SoC- 303 * specific clock code. 304 * 305 * @param periph_id peripheral to query 306 * @param mux_bits Set to number of bits in mux register 307 * @param divider_bits Set to the relevant MASK_BITS_* value 308 * @param type Set to the SoC-specific clock type 309 * @return 0 on success, -1 on error 310 */ 311 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits, 312 int *divider_bits, int *type); 313 314 /* 315 * Given a peripheral ID and clock source mux value, determine the clock_id 316 * of that peripheral's parent. 317 * 318 * This is an internal API between the core Tegra clock code and the SoC- 319 * specific clock code. 320 * 321 * @param periph_id peripheral to query 322 * @param source raw clock source mux value 323 * @return the CLOCK_ID_* value @source represents 324 */ 325 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source); 326 327 /** 328 * Given a peripheral ID and the required source clock, this returns which 329 * value should be programmed into the source mux for that peripheral. 330 * 331 * There is special code here to handle the one source type with 5 sources. 332 * 333 * @param periph_id peripheral to start 334 * @param source PLL id of required parent clock 335 * @param mux_bits Set to number of bits in mux register: 2 or 4 336 * @param divider_bits Set to number of divider bits (8 or 16) 337 * @return mux value (0-4, or -1 if not found) 338 */ 339 int get_periph_clock_source(enum periph_id periph_id, 340 enum clock_id parent, int *mux_bits, int *divider_bits); 341 342 /* 343 * Convert a device tree clock ID to our peripheral ID. They are mostly 344 * the same but we are very cautious so we check that a valid clock ID is 345 * provided. 346 * 347 * @param clk_id Clock ID according to tegra30 device tree binding 348 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 349 */ 350 enum periph_id clk_id_to_periph_id(int clk_id); 351 352 /** 353 * Set the output frequency you want for each PLL clock. 354 * PLL output frequencies are programmed by setting their N, M and P values. 355 * The governing equations are: 356 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 357 * where Fo is the output frequency from the PLL. 358 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 359 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 360 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 361 * 362 * @param n PLL feedback divider(DIVN) 363 * @param m PLL input divider(DIVN) 364 * @param p post divider(DIVP) 365 * @param cpcon base PLL charge pump(CPCON) 366 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 367 * be overridden), 1 if PLL is already correct 368 */ 369 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 370 371 /* return 1 if a peripheral ID is in range */ 372 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 373 (id) < CLOCK_TYPE_COUNT) 374 375 /* return 1 if a periphc_internal_id is in range */ 376 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 377 (id) < PERIPHC_COUNT) 378 379 /* SoC-specific TSC init */ 380 void arch_timer_init(void); 381 382 void tegra30_set_up_pllp(void); 383 384 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */ 385 #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3) 386 387 struct clk_pll_info { 388 u32 m_shift:5; /* DIVM_SHIFT */ 389 u32 n_shift:5; /* DIVN_SHIFT */ 390 u32 p_shift:5; /* DIVP_SHIFT */ 391 u32 kcp_shift:5; /* KCP/cpcon SHIFT */ 392 u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ 393 u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ 394 u32 rsvd:1; 395 u32 m_mask:10; /* DIVM_MASK */ 396 u32 n_mask:12; /* DIVN_MASK */ 397 u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ 398 u32 kcp_mask:10; /* KCP/CPCON MASK */ 399 u32 kvco_mask:10; /* KVCO/LFCON MASK */ 400 u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ 401 u32 rsvd2:6; 402 }; 403 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; 404 405 struct periph_clk_init { 406 enum periph_id periph_id; 407 enum clock_id parent_clock_id; 408 }; 409 extern struct periph_clk_init periph_clk_init_table[]; 410 411 /** 412 * Enable output clock for external peripherals 413 * 414 * @param clk_id Clock ID to output (1, 2 or 3) 415 * @return 0 if OK. -ve on error 416 */ 417 int clock_external_output(int clk_id); 418 419 #endif /* _TEGRA_CLOCK_H_ */ 420