1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * See file CREDITS for list of people who contributed to this 4 * project. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * MA 02111-1307 USA 20 */ 21 22 /* Tegra clock control functions */ 23 24 #ifndef _TEGRA_CLOCK_H_ 25 #define _TEGRA_CLOCK_H_ 26 27 /* Set of oscillator frequencies supported in the internal API. */ 28 enum clock_osc_freq { 29 /* All in MHz, so 13_0 is 13.0MHz */ 30 CLOCK_OSC_FREQ_13_0, 31 CLOCK_OSC_FREQ_19_2, 32 CLOCK_OSC_FREQ_12_0, 33 CLOCK_OSC_FREQ_26_0, 34 35 CLOCK_OSC_FREQ_COUNT, 36 }; 37 38 #include <asm/arch/clock-tables.h> 39 /* PLL stabilization delay in usec */ 40 #define CLOCK_PLL_STABLE_DELAY_US 300 41 42 /* return the current oscillator clock frequency */ 43 enum clock_osc_freq clock_get_osc_freq(void); 44 45 /** 46 * Start PLL using the provided configuration parameters. 47 * 48 * @param id clock id 49 * @param divm input divider 50 * @param divn feedback divider 51 * @param divp post divider 2^n 52 * @param cpcon charge pump setup control 53 * @param lfcon loop filter setup control 54 * 55 * @returns monotonic time in us that the PLL will be stable 56 */ 57 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 58 u32 divp, u32 cpcon, u32 lfcon); 59 60 /** 61 * Set PLL output frequency 62 * 63 * @param clkid clock id 64 * @param pllout pll output id 65 * @param rate desired output rate 66 * 67 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 68 */ 69 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 70 unsigned rate); 71 72 /** 73 * Read low-level parameters of a PLL. 74 * 75 * @param id clock id to read (note: USB is not supported) 76 * @param divm returns input divider 77 * @param divn returns feedback divider 78 * @param divp returns post divider 2^n 79 * @param cpcon returns charge pump setup control 80 * @param lfcon returns loop filter setup control 81 * 82 * @returns 0 if ok, -1 on error (invalid clock id) 83 */ 84 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 85 u32 *divp, u32 *cpcon, u32 *lfcon); 86 87 /* 88 * Enable a clock 89 * 90 * @param id clock id 91 */ 92 void clock_enable(enum periph_id clkid); 93 94 /* 95 * Disable a clock 96 * 97 * @param id clock id 98 */ 99 void clock_disable(enum periph_id clkid); 100 101 /* 102 * Set whether a clock is enabled or disabled. 103 * 104 * @param id clock id 105 * @param enable 1 to enable, 0 to disable 106 */ 107 void clock_set_enable(enum periph_id clkid, int enable); 108 109 /** 110 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 111 * it out of reset and waits for th delay again. 112 * 113 * @param periph_id peripheral to reset 114 * @param us_delay time to delay in microseconds 115 */ 116 void reset_periph(enum periph_id periph_id, int us_delay); 117 118 /** 119 * Put a peripheral into or out of reset. 120 * 121 * @param periph_id peripheral to reset 122 * @param enable 1 to put into reset, 0 to take out of reset 123 */ 124 void reset_set_enable(enum periph_id periph_id, int enable); 125 126 127 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 128 enum crc_reset_id { 129 /* Things we can hold in reset for each CPU */ 130 crc_rst_cpu = 1, 131 crc_rst_de = 1 << 2, /* What is de? */ 132 crc_rst_watchdog = 1 << 3, 133 crc_rst_debug = 1 << 4, 134 }; 135 136 /** 137 * Put parts of the CPU complex into or out of reset.\ 138 * 139 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 140 * @param which which parts of the complex to affect (OR of crc_reset_id) 141 * @param reset 1 to assert reset, 0 to de-assert 142 */ 143 void reset_cmplx_set_enable(int cpu, int which, int reset); 144 145 /** 146 * Set the source for a peripheral clock. This plus the divisor sets the 147 * clock rate. You need to look up the datasheet to see the meaning of the 148 * source parameter as it changes for each peripheral. 149 * 150 * Warning: This function is only for use pre-relocation. Please use 151 * clock_start_periph_pll() instead. 152 * 153 * @param periph_id peripheral to adjust 154 * @param source source clock (0, 1, 2 or 3) 155 */ 156 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 157 158 /** 159 * Set the source and divisor for a peripheral clock. This sets the 160 * clock rate. You need to look up the datasheet to see the meaning of the 161 * source parameter as it changes for each peripheral. 162 * 163 * Warning: This function is only for use pre-relocation. Please use 164 * clock_start_periph_pll() instead. 165 * 166 * @param periph_id peripheral to adjust 167 * @param source source clock (0, 1, 2 or 3) 168 * @param divisor divisor value to use 169 */ 170 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 171 unsigned divisor); 172 173 /** 174 * Start a peripheral PLL clock at the given rate. This also resets the 175 * peripheral. 176 * 177 * @param periph_id peripheral to start 178 * @param parent PLL id of required parent clock 179 * @param rate Required clock rate in Hz 180 * @return rate selected in Hz, or -1U if something went wrong 181 */ 182 unsigned clock_start_periph_pll(enum periph_id periph_id, 183 enum clock_id parent, unsigned rate); 184 185 /** 186 * Returns the rate of a peripheral clock in Hz. Since the caller almost 187 * certainly knows the parent clock (having just set it) we require that 188 * this be passed in so we don't need to work it out. 189 * 190 * @param periph_id peripheral to start 191 * @param parent PLL id of parent clock (used to calculate rate, you 192 * must know this!) 193 * @return clock rate of peripheral in Hz 194 */ 195 unsigned long clock_get_periph_rate(enum periph_id periph_id, 196 enum clock_id parent); 197 198 /** 199 * Adjust peripheral PLL clock to the given rate. This does not reset the 200 * peripheral. If a second stage divisor is not available, pass NULL for 201 * extra_div. If it is available, then this parameter will return the 202 * divisor selected (which will be a power of 2 from 1 to 256). 203 * 204 * @param periph_id peripheral to start 205 * @param parent PLL id of required parent clock 206 * @param rate Required clock rate in Hz 207 * @param extra_div value for the second-stage divisor (NULL if one is 208 not available) 209 * @return rate selected in Hz, or -1U if something went wrong 210 */ 211 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 212 enum clock_id parent, unsigned rate, int *extra_div); 213 214 /** 215 * Returns the clock rate of a specified clock, in Hz. 216 * 217 * @param parent PLL id of clock to check 218 * @return rate of clock in Hz 219 */ 220 unsigned clock_get_rate(enum clock_id clkid); 221 222 /** 223 * Start up a UART using low-level calls 224 * 225 * Prior to relocation clock_start_periph_pll() cannot be called. This 226 * function provides a way to set up a UART using low-level calls which 227 * do not require BSS. 228 * 229 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 230 */ 231 void clock_ll_start_uart(enum periph_id periph_id); 232 233 /** 234 * Decode a peripheral ID from a device tree node. 235 * 236 * This works by looking up the peripheral's 'clocks' node and reading out 237 * the second cell, which is the clock number / peripheral ID. 238 * 239 * @param blob FDT blob to use 240 * @param node Node to look at 241 * @return peripheral ID, or PERIPH_ID_NONE if none 242 */ 243 enum periph_id clock_decode_periph_id(const void *blob, int node); 244 245 /** 246 * Checks if the oscillator bypass is enabled (XOBP bit) 247 * 248 * @return 1 if bypass is enabled, 0 if not 249 */ 250 int clock_get_osc_bypass(void); 251 252 /* 253 * Checks that clocks are valid and prints a warning if not 254 * 255 * @return 0 if ok, -1 on error 256 */ 257 int clock_verify(void); 258 259 /* Initialize the clocks */ 260 void clock_init(void); 261 262 /* Initialize the PLLs */ 263 void clock_early_init(void); 264 265 /* Returns a pointer to the clock source register for a peripheral */ 266 u32 *get_periph_source_reg(enum periph_id periph_id); 267 268 /** 269 * Given a peripheral ID and the required source clock, this returns which 270 * value should be programmed into the source mux for that peripheral. 271 * 272 * There is special code here to handle the one source type with 5 sources. 273 * 274 * @param periph_id peripheral to start 275 * @param source PLL id of required parent clock 276 * @param mux_bits Set to number of bits in mux register: 2 or 4 277 * @param divider_bits Set to number of divider bits (8 or 16) 278 * @return mux value (0-4, or -1 if not found) 279 */ 280 int get_periph_clock_source(enum periph_id periph_id, 281 enum clock_id parent, int *mux_bits, int *divider_bits); 282 283 /* 284 * Convert a device tree clock ID to our peripheral ID. They are mostly 285 * the same but we are very cautious so we check that a valid clock ID is 286 * provided. 287 * 288 * @param clk_id Clock ID according to tegra30 device tree binding 289 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 290 */ 291 enum periph_id clk_id_to_periph_id(int clk_id); 292 293 /** 294 * Set the output frequency you want for each PLL clock. 295 * PLL output frequencies are programmed by setting their N, M and P values. 296 * The governing equations are: 297 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 298 * where Fo is the output frequency from the PLL. 299 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 300 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 301 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 302 * 303 * @param n PLL feedback divider(DIVN) 304 * @param m PLL input divider(DIVN) 305 * @param p post divider(DIVP) 306 * @param cpcon base PLL charge pump(CPCON) 307 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 308 * be overriden), 1 if PLL is already correct 309 */ 310 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 311 312 /* return 1 if a peripheral ID is in range */ 313 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 314 (id) < CLOCK_TYPE_COUNT) 315 316 /* return 1 if a periphc_internal_id is in range */ 317 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 318 (id) < PERIPHC_COUNT) 319 320 /* SoC-specific TSC init */ 321 void arch_timer_init(void); 322 323 #endif /* _TEGRA_CLOCK_H_ */ 324