1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /* Tegra clock control functions */
8 
9 #ifndef _TEGRA_CLOCK_H_
10 #define _TEGRA_CLOCK_H_
11 
12 /* Set of oscillator frequencies supported in the internal API. */
13 enum clock_osc_freq {
14 	/* All in MHz, so 13_0 is 13.0MHz */
15 	CLOCK_OSC_FREQ_13_0,
16 	CLOCK_OSC_FREQ_19_2,
17 	CLOCK_OSC_FREQ_12_0,
18 	CLOCK_OSC_FREQ_26_0,
19 	CLOCK_OSC_FREQ_38_4,
20 	CLOCK_OSC_FREQ_48_0,
21 
22 	CLOCK_OSC_FREQ_COUNT,
23 };
24 
25 /*
26  * Note that no Tegra clock register actually uses all of bits 31:28 as
27  * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
28  * those cases, nothing is stored in the bits about the mux field, so it's
29  * safe to pretend that the mux field extends all the way to the end of the
30  * register. As such, the U-Boot clock driver is currently a bit lazy, and
31  * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
32  * them all together and pretends they're all 31:28.
33  */
34 enum {
35 	MASK_BITS_31_30,
36 	MASK_BITS_31_29,
37 	MASK_BITS_31_28,
38 };
39 
40 #include <asm/arch/clock-tables.h>
41 /* PLL stabilization delay in usec */
42 #define CLOCK_PLL_STABLE_DELAY_US 300
43 
44 /* return the current oscillator clock frequency */
45 enum clock_osc_freq clock_get_osc_freq(void);
46 
47 /* return the clk_m frequency */
48 unsigned int clk_m_get_rate(unsigned int parent_rate);
49 
50 /**
51  * Start PLL using the provided configuration parameters.
52  *
53  * @param id	clock id
54  * @param divm	input divider
55  * @param divn	feedback divider
56  * @param divp	post divider 2^n
57  * @param cpcon	charge pump setup control
58  * @param lfcon	loop filter setup control
59  *
60  * @returns monotonic time in us that the PLL will be stable
61  */
62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
63 		u32 divp, u32 cpcon, u32 lfcon);
64 
65 /**
66  * Set PLL output frequency
67  *
68  * @param clkid	clock id
69  * @param pllout	pll output id
70  * @param rate		desired output rate
71  *
72  * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
73  */
74 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
75 		unsigned rate);
76 
77 /**
78  * Read low-level parameters of a PLL.
79  *
80  * @param id	clock id to read (note: USB is not supported)
81  * @param divm	returns input divider
82  * @param divn	returns feedback divider
83  * @param divp	returns post divider 2^n
84  * @param cpcon	returns charge pump setup control
85  * @param lfcon	returns loop filter setup control
86  *
87  * @returns 0 if ok, -1 on error (invalid clock id)
88  */
89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
90 		u32 *divp, u32 *cpcon, u32 *lfcon);
91 
92 /*
93  * Enable a clock
94  *
95  * @param id	clock id
96  */
97 void clock_enable(enum periph_id clkid);
98 
99 /*
100  * Disable a clock
101  *
102  * @param id	clock id
103  */
104 void clock_disable(enum periph_id clkid);
105 
106 /*
107  * Set whether a clock is enabled or disabled.
108  *
109  * @param id		clock id
110  * @param enable	1 to enable, 0 to disable
111  */
112 void clock_set_enable(enum periph_id clkid, int enable);
113 
114 /**
115  * Reset a peripheral. This puts it in reset, waits for a delay, then takes
116  * it out of reset and waits for th delay again.
117  *
118  * @param periph_id	peripheral to reset
119  * @param us_delay	time to delay in microseconds
120  */
121 void reset_periph(enum periph_id periph_id, int us_delay);
122 
123 /**
124  * Put a peripheral into or out of reset.
125  *
126  * @param periph_id	peripheral to reset
127  * @param enable	1 to put into reset, 0 to take out of reset
128  */
129 void reset_set_enable(enum periph_id periph_id, int enable);
130 
131 
132 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
133 enum crc_reset_id {
134 	/* Things we can hold in reset for each CPU */
135 	crc_rst_cpu = 1,
136 	crc_rst_de = 1 << 4,	/* What is de? */
137 	crc_rst_watchdog = 1 << 8,
138 	crc_rst_debug = 1 << 12,
139 };
140 
141 /**
142  * Put parts of the CPU complex into or out of reset.\
143  *
144  * @param cpu		cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
145  * @param which		which parts of the complex to affect (OR of crc_reset_id)
146  * @param reset		1 to assert reset, 0 to de-assert
147  */
148 void reset_cmplx_set_enable(int cpu, int which, int reset);
149 
150 /**
151  * Set the source for a peripheral clock. This plus the divisor sets the
152  * clock rate. You need to look up the datasheet to see the meaning of the
153  * source parameter as it changes for each peripheral.
154  *
155  * Warning: This function is only for use pre-relocation. Please use
156  * clock_start_periph_pll() instead.
157  *
158  * @param periph_id	peripheral to adjust
159  * @param source	source clock (0, 1, 2 or 3)
160  */
161 void clock_ll_set_source(enum periph_id periph_id, unsigned source);
162 
163 /**
164  * This function is similar to clock_ll_set_source() except that it can be
165  * used for clocks with more than 2 mux bits.
166  *
167  * @param periph_id	peripheral to adjust
168  * @param mux_bits	number of mux bits for the clock
169  * @param source	source clock (0-15 depending on mux_bits)
170  */
171 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
172 			     unsigned source);
173 
174 /**
175  * Set the source and divisor for a peripheral clock. This sets the
176  * clock rate. You need to look up the datasheet to see the meaning of the
177  * source parameter as it changes for each peripheral.
178  *
179  * Warning: This function is only for use pre-relocation. Please use
180  * clock_start_periph_pll() instead.
181  *
182  * @param periph_id	peripheral to adjust
183  * @param source	source clock (0, 1, 2 or 3)
184  * @param divisor	divisor value to use
185  */
186 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
187 		unsigned divisor);
188 
189 /**
190  * Start a peripheral PLL clock at the given rate. This also resets the
191  * peripheral.
192  *
193  * @param periph_id	peripheral to start
194  * @param parent	PLL id of required parent clock
195  * @param rate		Required clock rate in Hz
196  * @return rate selected in Hz, or -1U if something went wrong
197  */
198 unsigned clock_start_periph_pll(enum periph_id periph_id,
199 		enum clock_id parent, unsigned rate);
200 
201 /**
202  * Returns the rate of a peripheral clock in Hz. Since the caller almost
203  * certainly knows the parent clock (having just set it) we require that
204  * this be passed in so we don't need to work it out.
205  *
206  * @param periph_id	peripheral to start
207  * @param parent	PLL id of parent clock (used to calculate rate, you
208  *			must know this!)
209  * @return clock rate of peripheral in Hz
210  */
211 unsigned long clock_get_periph_rate(enum periph_id periph_id,
212 		enum clock_id parent);
213 
214 /**
215  * Adjust peripheral PLL clock to the given rate. This does not reset the
216  * peripheral. If a second stage divisor is not available, pass NULL for
217  * extra_div. If it is available, then this parameter will return the
218  * divisor selected (which will be a power of 2 from 1 to 256).
219  *
220  * @param periph_id	peripheral to start
221  * @param parent	PLL id of required parent clock
222  * @param rate		Required clock rate in Hz
223  * @param extra_div	value for the second-stage divisor (NULL if one is
224 			not available)
225  * @return rate selected in Hz, or -1U if something went wrong
226  */
227 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
228 		enum clock_id parent, unsigned rate, int *extra_div);
229 
230 /**
231  * Returns the clock rate of a specified clock, in Hz.
232  *
233  * @param parent	PLL id of clock to check
234  * @return rate of clock in Hz
235  */
236 unsigned clock_get_rate(enum clock_id clkid);
237 
238 /**
239  * Start up a UART using low-level calls
240  *
241  * Prior to relocation clock_start_periph_pll() cannot be called. This
242  * function provides a way to set up a UART using low-level calls which
243  * do not require BSS.
244  *
245  * @param periph_id	Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
246  */
247 void clock_ll_start_uart(enum periph_id periph_id);
248 
249 /**
250  * Decode a peripheral ID from a device tree node.
251  *
252  * This works by looking up the peripheral's 'clocks' node and reading out
253  * the second cell, which is the clock number / peripheral ID.
254  *
255  * @param blob		FDT blob to use
256  * @param node		Node to look at
257  * @return peripheral ID, or PERIPH_ID_NONE if none
258  */
259 enum periph_id clock_decode_periph_id(const void *blob, int node);
260 
261 /**
262  * Checks if the oscillator bypass is enabled (XOBP bit)
263  *
264  * @return 1 if bypass is enabled, 0 if not
265  */
266 int clock_get_osc_bypass(void);
267 
268 /*
269  * Checks that clocks are valid and prints a warning if not
270  *
271  * @return 0 if ok, -1 on error
272  */
273 int clock_verify(void);
274 
275 /* Initialize the clocks */
276 void clock_init(void);
277 
278 /* Initialize the PLLs */
279 void clock_early_init(void);
280 
281 /* Returns a pointer to the clock source register for a peripheral */
282 u32 *get_periph_source_reg(enum periph_id periph_id);
283 
284 /* Returns a pointer to the given 'simple' PLL */
285 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
286 
287 /**
288  * Given a peripheral ID and the required source clock, this returns which
289  * value should be programmed into the source mux for that peripheral.
290  *
291  * There is special code here to handle the one source type with 5 sources.
292  *
293  * @param periph_id     peripheral to start
294  * @param source        PLL id of required parent clock
295  * @param mux_bits      Set to number of bits in mux register: 2 or 4
296  * @param divider_bits  Set to number of divider bits (8 or 16)
297  * @return mux value (0-4, or -1 if not found)
298  */
299 int get_periph_clock_source(enum periph_id periph_id,
300 		enum clock_id parent, int *mux_bits, int *divider_bits);
301 
302 /*
303  * Convert a device tree clock ID to our peripheral ID. They are mostly
304  * the same but we are very cautious so we check that a valid clock ID is
305  * provided.
306  *
307  * @param clk_id        Clock ID according to tegra30 device tree binding
308  * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
309  */
310 enum periph_id clk_id_to_periph_id(int clk_id);
311 
312 /**
313  * Set the output frequency you want for each PLL clock.
314  * PLL output frequencies are programmed by setting their N, M and P values.
315  * The governing equations are:
316  *     VCO = (Fi / m) * n, Fo = VCO / (2^p)
317  *     where Fo is the output frequency from the PLL.
318  * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
319  *     216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
320  * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
321  *
322  * @param n PLL feedback divider(DIVN)
323  * @param m PLL input divider(DIVN)
324  * @param p post divider(DIVP)
325  * @param cpcon base PLL charge pump(CPCON)
326  * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
327  *              be overriden), 1 if PLL is already correct
328  */
329 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
330 
331 /* return 1 if a peripheral ID is in range */
332 #define clock_type_id_isvalid(id) ((id) >= 0 && \
333 		(id) < CLOCK_TYPE_COUNT)
334 
335 /* return 1 if a periphc_internal_id is in range */
336 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
337 		(id) < PERIPHC_COUNT)
338 
339 /* SoC-specific TSC init */
340 void arch_timer_init(void);
341 
342 void tegra30_set_up_pllp(void);
343 
344 /* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
345 #define CLOCK_ID_PLL_COUNT	(CLOCK_ID_COUNT - 3)
346 
347 struct clk_pll_info {
348 	u32	m_shift:5;	/* DIVM_SHIFT */
349 	u32	n_shift:5;	/* DIVN_SHIFT */
350 	u32	p_shift:5;	/* DIVP_SHIFT */
351 	u32	kcp_shift:5;	/* KCP/cpcon SHIFT */
352 	u32	kvco_shift:5;	/* KVCO/lfcon SHIFT */
353 	u32	lock_ena:6;	/* LOCK_ENABLE/EN_LOCKDET shift */
354 	u32	rsvd:1;
355 	u32	m_mask:10;	/* DIVM_MASK */
356 	u32	n_mask:12;	/* DIVN_MASK */
357 	u32	p_mask:10;	/* DIVP_MASK or VCO_MASK */
358 	u32	kcp_mask:10;	/* KCP/CPCON MASK */
359 	u32	kvco_mask:10;	/* KVCO/LFCON MASK */
360 	u32	lock_det:6;	/* LOCK_DETECT/LOCKED shift */
361 	u32	rsvd2:6;
362 };
363 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
364 
365 /**
366  * Enable output clock for external peripherals
367  *
368  * @param clk_id	Clock ID to output (1, 2 or 3)
369  * @return 0 if OK. -ve on error
370  */
371 int clock_external_output(int clk_id);
372 
373 #endif  /* _TEGRA_CLOCK_H_ */
374