1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* Tegra clock control functions */ 8 9 #ifndef _TEGRA_CLOCK_H_ 10 #define _TEGRA_CLOCK_H_ 11 12 /* Set of oscillator frequencies supported in the internal API. */ 13 enum clock_osc_freq { 14 /* All in MHz, so 13_0 is 13.0MHz */ 15 CLOCK_OSC_FREQ_13_0, 16 CLOCK_OSC_FREQ_19_2, 17 CLOCK_OSC_FREQ_12_0, 18 CLOCK_OSC_FREQ_26_0, 19 CLOCK_OSC_FREQ_38_4, 20 CLOCK_OSC_FREQ_48_0, 21 22 CLOCK_OSC_FREQ_COUNT, 23 }; 24 25 /* 26 * Note that no Tegra clock register actually uses all of bits 31:28 as 27 * the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in 28 * those cases, nothing is stored in the bits about the mux field, so it's 29 * safe to pretend that the mux field extends all the way to the end of the 30 * register. As such, the U-Boot clock driver is currently a bit lazy, and 31 * doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps 32 * them all together and pretends they're all 31:28. 33 */ 34 enum { 35 MASK_BITS_31_30, 36 MASK_BITS_31_29, 37 MASK_BITS_31_28, 38 }; 39 40 #include <asm/arch/clock-tables.h> 41 /* PLL stabilization delay in usec */ 42 #define CLOCK_PLL_STABLE_DELAY_US 300 43 44 /* return the current oscillator clock frequency */ 45 enum clock_osc_freq clock_get_osc_freq(void); 46 47 /** 48 * Start PLL using the provided configuration parameters. 49 * 50 * @param id clock id 51 * @param divm input divider 52 * @param divn feedback divider 53 * @param divp post divider 2^n 54 * @param cpcon charge pump setup control 55 * @param lfcon loop filter setup control 56 * 57 * @returns monotonic time in us that the PLL will be stable 58 */ 59 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, 60 u32 divp, u32 cpcon, u32 lfcon); 61 62 /** 63 * Set PLL output frequency 64 * 65 * @param clkid clock id 66 * @param pllout pll output id 67 * @param rate desired output rate 68 * 69 * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) 70 */ 71 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, 72 unsigned rate); 73 74 /** 75 * Read low-level parameters of a PLL. 76 * 77 * @param id clock id to read (note: USB is not supported) 78 * @param divm returns input divider 79 * @param divn returns feedback divider 80 * @param divp returns post divider 2^n 81 * @param cpcon returns charge pump setup control 82 * @param lfcon returns loop filter setup control 83 * 84 * @returns 0 if ok, -1 on error (invalid clock id) 85 */ 86 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, 87 u32 *divp, u32 *cpcon, u32 *lfcon); 88 89 /* 90 * Enable a clock 91 * 92 * @param id clock id 93 */ 94 void clock_enable(enum periph_id clkid); 95 96 /* 97 * Disable a clock 98 * 99 * @param id clock id 100 */ 101 void clock_disable(enum periph_id clkid); 102 103 /* 104 * Set whether a clock is enabled or disabled. 105 * 106 * @param id clock id 107 * @param enable 1 to enable, 0 to disable 108 */ 109 void clock_set_enable(enum periph_id clkid, int enable); 110 111 /** 112 * Reset a peripheral. This puts it in reset, waits for a delay, then takes 113 * it out of reset and waits for th delay again. 114 * 115 * @param periph_id peripheral to reset 116 * @param us_delay time to delay in microseconds 117 */ 118 void reset_periph(enum periph_id periph_id, int us_delay); 119 120 /** 121 * Put a peripheral into or out of reset. 122 * 123 * @param periph_id peripheral to reset 124 * @param enable 1 to put into reset, 0 to take out of reset 125 */ 126 void reset_set_enable(enum periph_id periph_id, int enable); 127 128 129 /* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */ 130 enum crc_reset_id { 131 /* Things we can hold in reset for each CPU */ 132 crc_rst_cpu = 1, 133 crc_rst_de = 1 << 4, /* What is de? */ 134 crc_rst_watchdog = 1 << 8, 135 crc_rst_debug = 1 << 12, 136 }; 137 138 /** 139 * Put parts of the CPU complex into or out of reset.\ 140 * 141 * @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3) 142 * @param which which parts of the complex to affect (OR of crc_reset_id) 143 * @param reset 1 to assert reset, 0 to de-assert 144 */ 145 void reset_cmplx_set_enable(int cpu, int which, int reset); 146 147 /** 148 * Set the source for a peripheral clock. This plus the divisor sets the 149 * clock rate. You need to look up the datasheet to see the meaning of the 150 * source parameter as it changes for each peripheral. 151 * 152 * Warning: This function is only for use pre-relocation. Please use 153 * clock_start_periph_pll() instead. 154 * 155 * @param periph_id peripheral to adjust 156 * @param source source clock (0, 1, 2 or 3) 157 */ 158 void clock_ll_set_source(enum periph_id periph_id, unsigned source); 159 160 /** 161 * This function is similar to clock_ll_set_source() except that it can be 162 * used for clocks with more than 2 mux bits. 163 * 164 * @param periph_id peripheral to adjust 165 * @param mux_bits number of mux bits for the clock 166 * @param source source clock (0-15 depending on mux_bits) 167 */ 168 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits, 169 unsigned source); 170 171 /** 172 * Set the source and divisor for a peripheral clock. This sets the 173 * clock rate. You need to look up the datasheet to see the meaning of the 174 * source parameter as it changes for each peripheral. 175 * 176 * Warning: This function is only for use pre-relocation. Please use 177 * clock_start_periph_pll() instead. 178 * 179 * @param periph_id peripheral to adjust 180 * @param source source clock (0, 1, 2 or 3) 181 * @param divisor divisor value to use 182 */ 183 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source, 184 unsigned divisor); 185 186 /** 187 * Start a peripheral PLL clock at the given rate. This also resets the 188 * peripheral. 189 * 190 * @param periph_id peripheral to start 191 * @param parent PLL id of required parent clock 192 * @param rate Required clock rate in Hz 193 * @return rate selected in Hz, or -1U if something went wrong 194 */ 195 unsigned clock_start_periph_pll(enum periph_id periph_id, 196 enum clock_id parent, unsigned rate); 197 198 /** 199 * Returns the rate of a peripheral clock in Hz. Since the caller almost 200 * certainly knows the parent clock (having just set it) we require that 201 * this be passed in so we don't need to work it out. 202 * 203 * @param periph_id peripheral to start 204 * @param parent PLL id of parent clock (used to calculate rate, you 205 * must know this!) 206 * @return clock rate of peripheral in Hz 207 */ 208 unsigned long clock_get_periph_rate(enum periph_id periph_id, 209 enum clock_id parent); 210 211 /** 212 * Adjust peripheral PLL clock to the given rate. This does not reset the 213 * peripheral. If a second stage divisor is not available, pass NULL for 214 * extra_div. If it is available, then this parameter will return the 215 * divisor selected (which will be a power of 2 from 1 to 256). 216 * 217 * @param periph_id peripheral to start 218 * @param parent PLL id of required parent clock 219 * @param rate Required clock rate in Hz 220 * @param extra_div value for the second-stage divisor (NULL if one is 221 not available) 222 * @return rate selected in Hz, or -1U if something went wrong 223 */ 224 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id, 225 enum clock_id parent, unsigned rate, int *extra_div); 226 227 /** 228 * Returns the clock rate of a specified clock, in Hz. 229 * 230 * @param parent PLL id of clock to check 231 * @return rate of clock in Hz 232 */ 233 unsigned clock_get_rate(enum clock_id clkid); 234 235 /** 236 * Start up a UART using low-level calls 237 * 238 * Prior to relocation clock_start_periph_pll() cannot be called. This 239 * function provides a way to set up a UART using low-level calls which 240 * do not require BSS. 241 * 242 * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1) 243 */ 244 void clock_ll_start_uart(enum periph_id periph_id); 245 246 /** 247 * Decode a peripheral ID from a device tree node. 248 * 249 * This works by looking up the peripheral's 'clocks' node and reading out 250 * the second cell, which is the clock number / peripheral ID. 251 * 252 * @param blob FDT blob to use 253 * @param node Node to look at 254 * @return peripheral ID, or PERIPH_ID_NONE if none 255 */ 256 enum periph_id clock_decode_periph_id(const void *blob, int node); 257 258 /** 259 * Checks if the oscillator bypass is enabled (XOBP bit) 260 * 261 * @return 1 if bypass is enabled, 0 if not 262 */ 263 int clock_get_osc_bypass(void); 264 265 /* 266 * Checks that clocks are valid and prints a warning if not 267 * 268 * @return 0 if ok, -1 on error 269 */ 270 int clock_verify(void); 271 272 /* Initialize the clocks */ 273 void clock_init(void); 274 275 /* Initialize the PLLs */ 276 void clock_early_init(void); 277 278 /* Returns a pointer to the clock source register for a peripheral */ 279 u32 *get_periph_source_reg(enum periph_id periph_id); 280 281 /* Returns a pointer to the given 'simple' PLL */ 282 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid); 283 284 /** 285 * Given a peripheral ID and the required source clock, this returns which 286 * value should be programmed into the source mux for that peripheral. 287 * 288 * There is special code here to handle the one source type with 5 sources. 289 * 290 * @param periph_id peripheral to start 291 * @param source PLL id of required parent clock 292 * @param mux_bits Set to number of bits in mux register: 2 or 4 293 * @param divider_bits Set to number of divider bits (8 or 16) 294 * @return mux value (0-4, or -1 if not found) 295 */ 296 int get_periph_clock_source(enum periph_id periph_id, 297 enum clock_id parent, int *mux_bits, int *divider_bits); 298 299 /* 300 * Convert a device tree clock ID to our peripheral ID. They are mostly 301 * the same but we are very cautious so we check that a valid clock ID is 302 * provided. 303 * 304 * @param clk_id Clock ID according to tegra30 device tree binding 305 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid 306 */ 307 enum periph_id clk_id_to_periph_id(int clk_id); 308 309 /** 310 * Set the output frequency you want for each PLL clock. 311 * PLL output frequencies are programmed by setting their N, M and P values. 312 * The governing equations are: 313 * VCO = (Fi / m) * n, Fo = VCO / (2^p) 314 * where Fo is the output frequency from the PLL. 315 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi) 316 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1 317 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming 318 * 319 * @param n PLL feedback divider(DIVN) 320 * @param m PLL input divider(DIVN) 321 * @param p post divider(DIVP) 322 * @param cpcon base PLL charge pump(CPCON) 323 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot 324 * be overriden), 1 if PLL is already correct 325 */ 326 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); 327 328 /* return 1 if a peripheral ID is in range */ 329 #define clock_type_id_isvalid(id) ((id) >= 0 && \ 330 (id) < CLOCK_TYPE_COUNT) 331 332 /* return 1 if a periphc_internal_id is in range */ 333 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \ 334 (id) < PERIPHC_COUNT) 335 336 /* SoC-specific TSC init */ 337 void arch_timer_init(void); 338 339 void tegra30_set_up_pllp(void); 340 341 /* Number of PLL-based clocks (i.e. not OSC or 32KHz) */ 342 #define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2) 343 344 struct clk_pll_info { 345 u32 m_shift:5; /* DIVM_SHIFT */ 346 u32 n_shift:5; /* DIVN_SHIFT */ 347 u32 p_shift:5; /* DIVP_SHIFT */ 348 u32 kcp_shift:5; /* KCP/cpcon SHIFT */ 349 u32 kvco_shift:5; /* KVCO/lfcon SHIFT */ 350 u32 lock_ena:6; /* LOCK_ENABLE/EN_LOCKDET shift */ 351 u32 rsvd:1; 352 u32 m_mask:10; /* DIVM_MASK */ 353 u32 n_mask:12; /* DIVN_MASK */ 354 u32 p_mask:10; /* DIVP_MASK or VCO_MASK */ 355 u32 kcp_mask:10; /* KCP/CPCON MASK */ 356 u32 kvco_mask:10; /* KVCO/LFCON MASK */ 357 u32 lock_det:6; /* LOCK_DETECT/LOCKED shift */ 358 u32 rsvd2:6; 359 }; 360 extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT]; 361 362 /** 363 * Enable output clock for external peripherals 364 * 365 * @param clk_id Clock ID to output (1, 2 or 3) 366 * @return 0 if OK. -ve on error 367 */ 368 int clock_external_output(int clk_id); 369 370 #endif /* _TEGRA_CLOCK_H_ */ 371