1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _TEGRA_CLK_RST_H_ 25 #define _TEGRA_CLK_RST_H_ 26 27 /* PLL registers - there are several PLLs in the clock controller */ 28 struct clk_pll { 29 uint pll_base; /* the control register */ 30 uint pll_out[2]; /* output control */ 31 uint pll_misc; /* other misc things */ 32 }; 33 34 /* PLL registers - there are several PLLs in the clock controller */ 35 struct clk_pll_simple { 36 uint pll_base; /* the control register */ 37 uint pll_misc; /* other misc things */ 38 }; 39 40 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ 41 struct clk_set_clr { 42 uint set; 43 uint clr; 44 }; 45 46 /* 47 * Most PLLs use the clk_pll structure, but some have a simpler two-member 48 * structure for which we use clk_pll_simple. The reason for this non- 49 * othogonal setup is not stated. 50 */ 51 enum { 52 TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ 53 TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ 54 TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ 55 TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ 56 TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ 57 TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W*/ 58 }; 59 60 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ 61 struct clk_rst_ctlr { 62 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ 63 uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ 64 uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ 65 uint crc_reserved0; /* reserved_0, 0x1C */ 66 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ 67 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ 68 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ 69 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ 70 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ 71 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ 72 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ 73 uint crc_reserved1; /* reserved_1, 0x3C */ 74 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ 75 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ 76 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ 77 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ 78 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ 79 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ 80 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ 81 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ 82 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ 83 84 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ 85 86 /* PLLs from 0xe0 to 0xf4 */ 87 struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; 88 89 uint crc_reserved10; /* _reserved_10, 0xF8 */ 90 uint crc_reserved11; /* _reserved_11, 0xFC */ 91 92 uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ 93 94 uint crc_reserved20[64]; /* _reserved_20, 0x200-2fc */ 95 96 /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ 97 struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; 98 99 uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ 100 101 /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ 102 struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; 103 104 uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */ 105 106 uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ 107 uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ 108 109 /* Additional (T30) registers */ 110 uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ 111 uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ 112 113 uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ 114 115 uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ 116 uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ 117 uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ 118 uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ 119 uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ 120 uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ 121 uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ 122 uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ 123 uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ 124 uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTR1L_0, 0x384 */ 125 uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ 126 uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ 127 uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* _G3D2_0..., 0x3b0-0x42c */ 128 /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ 129 struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; 130 /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ 131 struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; 132 /* Additional (T114) registers */ 133 uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */ 134 uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */ 135 uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */ 136 uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */ 137 uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ 138 uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ 139 uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ 140 uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ 141 uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ 142 uint crc_reserved40[1]; /* _reserved_40, 0x474 */ 143 uint crc_intstatus; /* __INTSTATUS_0, 0x478 */ 144 uint crc_intmask; /* __INTMASK_0, 0x47C */ 145 uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ 146 uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ 147 uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ 148 149 uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ 150 uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ 151 uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ 152 uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ 153 154 uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ 155 uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ 156 uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ 157 uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ 158 uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ 159 uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ 160 uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ 161 }; 162 163 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ 164 #define CPU3_CLK_STP_SHIFT 11 165 #define CPU2_CLK_STP_SHIFT 10 166 #define CPU1_CLK_STP_SHIFT 9 167 #define CPU0_CLK_STP_SHIFT 8 168 #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) 169 170 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */ 171 #define PLL_BYPASS_SHIFT 31 172 #define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) 173 174 #define PLL_ENABLE_SHIFT 30 175 #define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) 176 177 #define PLL_BASE_OVRRIDE_MASK (1U << 28) 178 179 #define PLL_DIVP_SHIFT 20 180 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) 181 182 #define PLL_DIVN_SHIFT 8 183 #define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) 184 185 #define PLL_DIVM_SHIFT 0 186 #define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) 187 188 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ 189 #define PLL_OUT_RSTN (1 << 0) 190 #define PLL_OUT_CLKEN (1 << 1) 191 #define PLL_OUT_OVRRIDE (1 << 2) 192 193 #define PLL_OUT_RATIO_SHIFT 8 194 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) 195 196 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */ 197 #define PLL_DCCON_SHIFT 20 198 #define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) 199 200 #define PLL_LOCK_ENABLE_SHIFT 18 201 #define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) 202 203 #define PLL_CPCON_SHIFT 8 204 #define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) 205 206 #define PLL_LFCON_SHIFT 4 207 #define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) 208 209 #define PLLU_VCO_FREQ_SHIFT 20 210 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) 211 212 #define PLLP_OUT1_OVR (1 << 2) 213 #define PLLP_OUT2_OVR (1 << 18) 214 #define PLLP_OUT3_OVR (1 << 2) 215 #define PLLP_OUT4_OVR (1 << 18) 216 #define PLLP_OUT1_RATIO 8 217 #define PLLP_OUT2_RATIO 24 218 #define PLLP_OUT3_RATIO 8 219 #define PLLP_OUT4_RATIO 24 220 221 enum { 222 IN_408_OUT_204_DIVISOR = 2, 223 IN_408_OUT_102_DIVISOR = 6, 224 IN_408_OUT_48_DIVISOR = 15, 225 IN_408_OUT_9_6_DIVISOR = 83, 226 }; 227 228 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 229 #define OSC_XOBP_SHIFT 1 230 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) 231 232 /* 233 * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits 234 * but can be 16. We could use knowledge we have to restrict the mask in 235 * the 8-bit cases (the divider_bits value returned by 236 * get_periph_clock_source()) but it does not seem worth it since the code 237 * already checks the ranges of values it is writing, in clk_get_divider(). 238 */ 239 #define OUT_CLK_DIVISOR_SHIFT 0 240 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) 241 242 #define OUT_CLK_SOURCE_SHIFT 30 243 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) 244 245 #define OUT_CLK_SOURCE4_SHIFT 28 246 #define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) 247 248 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ 249 #define SCLK_SYS_STATE_SHIFT 28U 250 #define SCLK_SYS_STATE_MASK (15U << SCLK_SYS_STATE_SHIFT) 251 enum { 252 SCLK_SYS_STATE_STDBY, 253 SCLK_SYS_STATE_IDLE, 254 SCLK_SYS_STATE_RUN, 255 SCLK_SYS_STATE_IRQ = 4U, 256 SCLK_SYS_STATE_FIQ = 8U, 257 }; 258 #define SCLK_COP_FIQ_MASK (1 << 27) 259 #define SCLK_CPU_FIQ_MASK (1 << 26) 260 #define SCLK_COP_IRQ_MASK (1 << 25) 261 #define SCLK_CPU_IRQ_MASK (1 << 24) 262 263 #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT 12 264 #define SCLK_SWAKEUP_FIQ_SOURCE_MASK \ 265 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) 266 #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT 8 267 #define SCLK_SWAKEUP_IRQ_SOURCE_MASK \ 268 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) 269 #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT 4 270 #define SCLK_SWAKEUP_RUN_SOURCE_MASK \ 271 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) 272 #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT 0 273 274 #define SCLK_SWAKEUP_IDLE_SOURCE_MASK \ 275 (7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) 276 enum { 277 SCLK_SOURCE_CLKM, 278 SCLK_SOURCE_PLLC_OUT1, 279 SCLK_SOURCE_PLLP_OUT4, 280 SCLK_SOURCE_PLLP_OUT3, 281 SCLK_SOURCE_PLLP_OUT2, 282 SCLK_SOURCE_CLKD, 283 SCLK_SOURCE_CLKS, 284 SCLK_SOURCE_PLLM_OUT1, 285 }; 286 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 (7 << 12) 287 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 (7 << 8) 288 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1 (7 << 4) 289 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 (7 << 0) 290 291 /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */ 292 #define SUPER_SCLK_ENB_SHIFT 31U 293 #define SUPER_SCLK_ENB_MASK (1U << 31) 294 #define SUPER_SCLK_DIVIDEND_SHIFT 8 295 #define SUPER_SCLK_DIVIDEND_MASK (0xff << SUPER_SCLK_DIVIDEND_SHIFT) 296 #define SUPER_SCLK_DIVISOR_SHIFT 0 297 #define SUPER_SCLK_DIVISOR_MASK (0xff << SUPER_SCLK_DIVISOR_SHIFT) 298 299 /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE */ 300 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7 301 #define CLK_SYS_RATE_HCLK_DISABLE_MASK (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) 302 #define CLK_SYS_RATE_AHB_RATE_SHIFT 4 303 #define CLK_SYS_RATE_AHB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) 304 #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3 305 #define CLK_SYS_RATE_PCLK_DISABLE_MASK (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) 306 #define CLK_SYS_RATE_APB_RATE_SHIFT 0 307 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) 308 309 /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR */ 310 #define CLR_CPURESET0 (1 << 0) 311 #define CLR_CPURESET1 (1 << 1) 312 #define CLR_CPURESET2 (1 << 2) 313 #define CLR_CPURESET3 (1 << 3) 314 #define CLR_DBGRESET0 (1 << 12) 315 #define CLR_DBGRESET1 (1 << 13) 316 #define CLR_DBGRESET2 (1 << 14) 317 #define CLR_DBGRESET3 (1 << 15) 318 #define CLR_CORERESET0 (1 << 16) 319 #define CLR_CORERESET1 (1 << 17) 320 #define CLR_CORERESET2 (1 << 18) 321 #define CLR_CORERESET3 (1 << 19) 322 #define CLR_CXRESET0 (1 << 20) 323 #define CLR_CXRESET1 (1 << 21) 324 #define CLR_CXRESET2 (1 << 22) 325 #define CLR_CXRESET3 (1 << 23) 326 #define CLR_NONCPURESET (1 << 29) 327 328 #endif /* _TEGRA_CLK_RST_H_ */ 329