1 /* 2 * (C) Copyright 2010,2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #ifndef _CLK_RST_H_ 25 #define _CLK_RST_H_ 26 27 /* PLL registers - there are several PLLs in the clock controller */ 28 struct clk_pll { 29 uint pll_base; /* the control register */ 30 uint pll_out[2]; /* output control */ 31 uint pll_misc; /* other misc things */ 32 }; 33 34 /* PLL registers - there are several PLLs in the clock controller */ 35 struct clk_pll_simple { 36 uint pll_base; /* the control register */ 37 uint pll_misc; /* other misc things */ 38 }; 39 40 /* 41 * Most PLLs use the clk_pll structure, but some have a simpler two-member 42 * structure for which we use clk_pll_simple. The reason for this non- 43 * othogonal setup is not stated. 44 */ 45 enum { 46 TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ 47 TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ 48 TEGRA_CLK_REGS = 3, /* Number of clock enable registers */ 49 TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */ 50 }; 51 52 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ 53 struct clk_rst_ctlr { 54 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */ 55 uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ 56 uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ 57 uint crc_reserved0; /* reserved_0, 0x1C */ 58 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */ 59 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ 60 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ 61 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ 62 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ 63 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */ 64 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */ 65 uint crc_reserved1; /* reserved_1, 0x3C */ 66 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ 67 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ 68 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ 69 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ 70 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ 71 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ 72 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ 73 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ 74 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ 75 76 struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ 77 78 /* PLLs from 0xe0 to 0xf4 */ 79 struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; 80 81 uint crc_reserved10; /* _reserved_10, 0xF8 */ 82 uint crc_reserved11; /* _reserved_11, 0xFC */ 83 84 uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ 85 uint crc_reserved20[80]; /* 0x200-33C */ 86 uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */ 87 uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */ 88 }; 89 90 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */ 91 #define CPU1_CLK_STP_SHIFT 9 92 93 #define CPU0_CLK_STP_SHIFT 8 94 #define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT) 95 96 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */ 97 #define PLL_BYPASS_SHIFT 31 98 #define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) 99 100 #define PLL_ENABLE_SHIFT 30 101 #define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) 102 103 #define PLL_BASE_OVRRIDE_MASK (1U << 28) 104 105 #define PLL_DIVP_SHIFT 20 106 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) 107 108 #define PLL_DIVN_SHIFT 8 109 #define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) 110 111 #define PLL_DIVM_SHIFT 0 112 #define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) 113 114 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ 115 #define PLL_OUT_RSTN (1 << 0) 116 #define PLL_OUT_CLKEN (1 << 1) 117 #define PLL_OUT_OVRRIDE (1 << 2) 118 119 #define PLL_OUT_RATIO_SHIFT 8 120 #define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT) 121 122 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */ 123 #define PLL_CPCON_SHIFT 8 124 #define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) 125 126 #define PLL_LFCON_SHIFT 4 127 #define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) 128 129 #define PLLU_VCO_FREQ_SHIFT 20 130 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) 131 132 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */ 133 #define OSC_FREQ_SHIFT 30 134 #define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT) 135 #define OSC_XOBP_SHIFT 1 136 #define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT) 137 138 /* 139 * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits 140 * but can be 16. We could use knowledge we have to restrict the mask in 141 * the 8-bit cases (the divider_bits value returned by 142 * get_periph_clock_source()) but it does not seem worth it since the code 143 * already checks the ranges of values it is writing, in clk_get_divider(). 144 */ 145 #define OUT_CLK_DIVISOR_SHIFT 0 146 #define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) 147 148 #define OUT_CLK_SOURCE_SHIFT 30 149 #define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) 150 151 #define OUT_CLK_SOURCE4_SHIFT 28 152 #define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) 153 154 #endif /* CLK_RST_H */ 155