1 /*
2  *  (C) Copyright 2010-2014
3  *  NVIDIA Corporation <www.nvidia.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _TEGRA_CLK_RST_H_
9 #define _TEGRA_CLK_RST_H_
10 
11 /* PLL registers - there are several PLLs in the clock controller */
12 struct clk_pll {
13 	uint pll_base;		/* the control register */
14 	/* pll_out[0] is output A control, pll_out[1] is output B control */
15 	uint pll_out[2];
16 	uint pll_misc;		/* other misc things */
17 };
18 
19 /* PLL registers - there are several PLLs in the clock controller */
20 struct clk_pll_simple {
21 	uint pll_base;		/* the control register */
22 	uint pll_misc;		/* other misc things */
23 };
24 
25 struct clk_pllm {
26 	uint pllm_base;		/* the control register */
27 	uint pllm_out;		/* output control */
28 	uint pllm_misc1;	/* misc1 */
29 	uint pllm_misc2;	/* misc2 */
30 };
31 
32 /* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */
33 struct clk_set_clr {
34 	uint set;
35 	uint clr;
36 };
37 
38 /*
39  * Most PLLs use the clk_pll structure, but some have a simpler two-member
40  * structure for which we use clk_pll_simple. The reason for this non-
41  * othogonal setup is not stated.
42  */
43 enum {
44 	TEGRA_CLK_PLLS		= 6,	/* Number of normal PLLs */
45 	TEGRA_CLK_SIMPLE_PLLS	= 3,	/* Number of simple PLLs */
46 	TEGRA_CLK_REGS		= 3,	/* Number of clock enable regs L/H/U */
47 	TEGRA_CLK_SOURCES	= 64,	/* Number of ppl clock sources L/H/U */
48 	TEGRA_CLK_REGS_VW	= 2,	/* Number of clock enable regs V/W */
49 	TEGRA_CLK_SOURCES_VW	= 32,	/* Number of ppl clock sources V/W */
50 	TEGRA_CLK_SOURCES_X	= 32,	/* Number of ppl clock sources X */
51 };
52 
53 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
54 struct clk_rst_ctlr {
55 	uint crc_rst_src;			/* _RST_SOURCE_0,0x00 */
56 	uint crc_rst_dev[TEGRA_CLK_REGS];	/* _RST_DEVICES_L/H/U_0 */
57 	uint crc_clk_out_enb[TEGRA_CLK_REGS];	/* _CLK_OUT_ENB_L/H/U_0 */
58 	uint crc_reserved0;		/* reserved_0,		0x1C */
59 	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0, 0x20 */
60 	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
61 	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
62 	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
63 	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
64 	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
65 	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
66 	uint crc_reserved1;		/* reserved_1,		0x3C */
67 	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
68 	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
69 	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
70 	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
71 	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
72 	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
73 	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
74 	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
75 	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
76 
77 	struct clk_pll crc_pll[TEGRA_CLK_PLLS];	/* PLLs from 0x80 to 0xdc */
78 
79 	/* PLLs from 0xe0 to 0xf4    */
80 	struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
81 
82 	uint crc_reserved10;		/* _reserved_10,	0xF8 */
83 	uint crc_reserved11;		/* _reserved_11,	0xFC */
84 
85 	uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0...	0x100-1fc */
86 
87 	uint crc_reserved20[32];	/* _reserved_20,	0x200-27c */
88 
89 	uint crc_clk_out_enb_x;		/* _CLK_OUT_ENB_X_0,	0x280 */
90 	uint crc_clk_enb_x_set;		/* _CLK_ENB_X_SET_0,	0x284 */
91 	uint crc_clk_enb_x_clr;		/* _CLK_ENB_X_CLR_0,	0x288 */
92 
93 	uint crc_rst_devices_x;		/* _RST_DEVICES_X_0,	0x28c */
94 	uint crc_rst_dev_x_set;		/* _RST_DEV_X_SET_0,	0x290 */
95 	uint crc_rst_dev_x_clr;		/* _RST_DEV_X_CLR_0,	0x294 */
96 
97 	uint crc_reserved21[23];	/* _reserved_21,	0x298-2f0 */
98 
99 	uint crc_dfll_base;		/* _DFLL_BASE_0,	0x2f4 */
100 
101 	uint crc_reserved22[2];		/* _reserved_22,	0x2f8-2fc */
102 
103 	/* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */
104 	struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS];
105 
106 	uint crc_reserved30[2];		/* _reserved_30,	0x318, 0x31c */
107 
108 	/* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */
109 	struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS];
110 
111 	uint crc_reserved31[2];		/* _reserved_31,	0x338, 0x33c */
112 
113 	uint crc_cpu_cmplx_set;		/* _RST_CPU_CMPLX_SET_0,    0x340 */
114 	uint crc_cpu_cmplx_clr;		/* _RST_CPU_CMPLX_CLR_0,    0x344 */
115 
116 	/* Additional (T30) registers */
117 	uint crc_clk_cpu_cmplx_set;	/* _CLK_CPU_CMPLX_SET_0,    0x348 */
118 	uint crc_clk_cpu_cmplx_clr;	/* _CLK_CPU_CMPLX_SET_0,    0x34c */
119 
120 	uint crc_reserved32[2];		/* _reserved_32,      0x350,0x354 */
121 
122 	uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
123 	uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
124 	uint crc_cclkg_brst_pol;	/* _CCLKG_BURST_POLICY_0,   0x368 */
125 	uint crc_super_cclkg_div;	/* _SUPER_CCLKG_DIVIDER_0,  0x36C */
126 	uint crc_cclklp_brst_pol;	/* _CCLKLP_BURST_POLICY_0,  0x370 */
127 	uint crc_super_cclkp_div;	/* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
128 	uint crc_clk_cpug_cmplx;	/* _CLK_CPUG_CMPLX_0,       0x378 */
129 	uint crc_clk_cpulp_cmplx;	/* _CLK_CPULP_CMPLX_0,      0x37C */
130 	uint crc_cpu_softrst_ctrl;	/* _CPU_SOFTRST_CTRL_0,     0x380 */
131 	uint crc_cpu_softrst_ctrl1;	/* _CPU_SOFTRST_CTRL1_0,    0x384 */
132 	uint crc_cpu_softrst_ctrl2;	/* _CPU_SOFTRST_CTRL2_0,    0x388 */
133 	uint crc_reserved33[9];		/* _reserved_33,        0x38c-3ac */
134 	uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW];	/* 0x3B0-0x42C */
135 	/* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */
136 	struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
137 	/* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
138 	struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
139 	/* Additional (T114) registers */
140 	uint crc_rst_cpug_cmplx_set;	/* _RST_CPUG_CMPLX_SET_0,  0x450 */
141 	uint crc_rst_cpug_cmplx_clr;	/* _RST_CPUG_CMPLX_CLR_0,  0x454 */
142 	uint crc_rst_cpulp_cmplx_set;	/* _RST_CPULP_CMPLX_SET_0, 0x458 */
143 	uint crc_rst_cpulp_cmplx_clr;	/* _RST_CPULP_CMPLX_CLR_0, 0x45C */
144 	uint crc_clk_cpug_cmplx_set;	/* _CLK_CPUG_CMPLX_SET_0,  0x460 */
145 	uint crc_clk_cpug_cmplx_clr;	/* _CLK_CPUG_CMPLX_CLR_0,  0x464 */
146 	uint crc_clk_cpulp_cmplx_set;	/* _CLK_CPULP_CMPLX_SET_0, 0x468 */
147 	uint crc_clk_cpulp_cmplx_clr;	/* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
148 	uint crc_cpu_cmplx_status;	/* _CPU_CMPLX_STATUS_0,    0x470 */
149 	uint crc_reserved40[1];		/* _reserved_40,        0x474 */
150 	uint crc_intstatus;		/* __INTSTATUS_0,       0x478 */
151 	uint crc_intmask;		/* __INTMASK_0,         0x47C */
152 	uint crc_utmip_pll_cfg0;	/* _UTMIP_PLL_CFG0_0,	0x480 */
153 	uint crc_utmip_pll_cfg1;	/* _UTMIP_PLL_CFG1_0,	0x484 */
154 	uint crc_utmip_pll_cfg2;	/* _UTMIP_PLL_CFG2_0,	0x488 */
155 
156 	uint crc_plle_aux;		/* _PLLE_AUX_0,		0x48C */
157 	uint crc_sata_pll_cfg0;		/* _SATA_PLL_CFG0_0,	0x490 */
158 	uint crc_sata_pll_cfg1;		/* _SATA_PLL_CFG1_0,	0x494 */
159 	uint crc_pcie_pll_cfg0;		/* _PCIE_PLL_CFG0_0,	0x498 */
160 
161 	uint crc_prog_audio_dly_clk;	/* _PROG_AUDIO_DLY_CLK_0, 0x49C */
162 	uint crc_audio_sync_clk_i2s0;	/* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
163 	uint crc_audio_sync_clk_i2s1;	/* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
164 	uint crc_audio_sync_clk_i2s2;	/* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
165 	uint crc_audio_sync_clk_i2s3;	/* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
166 	uint crc_audio_sync_clk_i2s4;	/* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
167 	uint crc_audio_sync_clk_spdif;	/* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
168 
169 	uint crc_plld2_base;		/* _PLLD2_BASE_0, 0x4B8 */
170 	uint crc_plld2_misc;		/* _PLLD2_MISC_0, 0x4BC */
171 	uint crc_utmip_pll_cfg3;	/* _UTMIP_PLL_CFG3_0, 0x4C0 */
172 	uint crc_pllrefe_base;		/* _PLLREFE_BASE_0, 0x4C4 */
173 	uint crc_pllrefe_misc;		/* _PLLREFE_MISC_0, 0x4C8 */
174 	uint crs_reserved_50[7];	/* _reserved_50, 0x4CC-0x4E4 */
175 	uint crc_pllc2_base;		/* _PLLC2_BASE_0, 0x4E8 */
176 	uint crc_pllc2_misc0;		/* _PLLC2_MISC_0_0, 0x4EC */
177 	uint crc_pllc2_misc1;		/* _PLLC2_MISC_1_0, 0x4F0 */
178 	uint crc_pllc2_misc2;		/* _PLLC2_MISC_2_0, 0x4F4 */
179 	uint crc_pllc2_misc3;		/* _PLLC2_MISC_3_0, 0x4F8 */
180 	uint crc_pllc3_base;		/* _PLLC3_BASE_0, 0x4FC */
181 	uint crc_pllc3_misc0;		/* _PLLC3_MISC_0_0, 0x500 */
182 	uint crc_pllc3_misc1;		/* _PLLC3_MISC_1_0, 0x504 */
183 	uint crc_pllc3_misc2;		/* _PLLC3_MISC_2_0, 0x508 */
184 	uint crc_pllc3_misc3;		/* _PLLC3_MISC_3_0, 0x50C */
185 	uint crc_pllx_misc1;		/* _PLLX_MISC_1_0, 0x510 */
186 	uint crc_pllx_misc2;		/* _PLLX_MISC_2_0, 0x514 */
187 	uint crc_pllx_misc3;		/* _PLLX_MISC_3_0, 0x518 */
188 	uint crc_xusbio_pll_cfg0;	/* _XUSBIO_PLL_CFG0_0, 0x51C */
189 	uint crc_xusbio_pll_cfg1;	/* _XUSBIO_PLL_CFG0_1, 0x520 */
190 	uint crc_plle_aux1;		/* _PLLE_AUX1_0, 0x524 */
191 	uint crc_pllp_reshift;		/* _PLLP_RESHIFT_0, 0x528 */
192 	uint crc_utmipll_hw_pwrdn_cfg0;	/* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
193 	uint crc_pllu_hw_pwrdn_cfg0;	/* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
194 	uint crc_xusb_pll_cfg0;		/* _XUSB_PLL_CFG0_0, 0x534 */
195 	uint crc_reserved51[1];		/* _reserved_51, 0x538 */
196 	uint crc_clk_cpu_misc;		/* _CLK_CPU_MISC_0, 0x53C */
197 	uint crc_clk_cpug_misc;		/* _CLK_CPUG_MISC_0, 0x540 */
198 	uint crc_clk_cpulp_misc;	/* _CLK_CPULP_MISC_0, 0x544 */
199 	uint crc_pllx_hw_ctrl_cfg;	/* _PLLX_HW_CTRL_CFG_0, 0x548 */
200 	uint crc_pllx_sw_ramp_cfg;	/* _PLLX_SW_RAMP_CFG_0, 0x54C */
201 	uint crc_pllx_hw_ctrl_status;	/* _PLLX_HW_CTRL_STATUS_0, 0x550 */
202 	uint crc_reserved52[1];		/* _reserved_52, 0x554 */
203 	uint crc_super_gr3d_clk_div;	/* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
204 	uint crc_spare_reg0;		/* _SPARE_REG0_0, 0x55C */
205 
206 	/* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
207 	uint crc_reserved60[40];	/* _reserved_60, 0x560 - 0x5FC */
208 	uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
209 };
210 
211 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
212 #define CPU3_CLK_STP_SHIFT	11
213 #define CPU2_CLK_STP_SHIFT	10
214 #define CPU1_CLK_STP_SHIFT	9
215 #define CPU0_CLK_STP_SHIFT	8
216 #define CPU0_CLK_STP_MASK	(1U << CPU0_CLK_STP_SHIFT)
217 
218 /* CLK_RST_CONTROLLER_PLLx_BASE_0 */
219 #define PLL_BYPASS_SHIFT	31
220 #define PLL_BYPASS_MASK		(1U << PLL_BYPASS_SHIFT)
221 
222 #define PLL_ENABLE_SHIFT	30
223 #define PLL_ENABLE_MASK		(1U << PLL_ENABLE_SHIFT)
224 
225 #define PLL_BASE_OVRRIDE_MASK	(1U << 28)
226 
227 #define PLL_LOCK_SHIFT		27
228 #define PLL_LOCK_MASK		(1U << PLL_LOCK_SHIFT)
229 
230 #define PLL_DIVP_SHIFT		20
231 #define PLL_DIVP_MASK		(7U << PLL_DIVP_SHIFT)
232 
233 #define PLL_DIVN_SHIFT		8
234 #define PLL_DIVN_MASK		(0x3ffU << PLL_DIVN_SHIFT)
235 
236 #define PLL_DIVM_SHIFT		0
237 #define PLL_DIVM_MASK		(0x1f << PLL_DIVM_SHIFT)
238 
239 /* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
240 #define PLL_OUT_RSTN		(1 << 0)
241 #define PLL_OUT_CLKEN		(1 << 1)
242 #define PLL_OUT_OVRRIDE		(1 << 2)
243 
244 #define PLL_OUT_RATIO_SHIFT	8
245 #define PLL_OUT_RATIO_MASK	(0xffU << PLL_OUT_RATIO_SHIFT)
246 
247 /* CLK_RST_CONTROLLER_PLLx_MISC_0 */
248 #define PLL_DCCON_SHIFT		20
249 #define PLL_DCCON_MASK		(1U << PLL_DCCON_SHIFT)
250 
251 #define PLL_LOCK_ENABLE_SHIFT	18
252 #define PLL_LOCK_ENABLE_MASK	(1U << PLL_LOCK_ENABLE_SHIFT)
253 
254 #define PLL_CPCON_SHIFT		8
255 #define PLL_CPCON_MASK		(15U << PLL_CPCON_SHIFT)
256 
257 #define PLL_LFCON_SHIFT		4
258 #define PLL_LFCON_MASK		(15U << PLL_LFCON_SHIFT)
259 
260 #define PLLU_VCO_FREQ_SHIFT	20
261 #define PLLU_VCO_FREQ_MASK	(1U << PLLU_VCO_FREQ_SHIFT)
262 
263 #define PLLP_OUT1_OVR		(1 << 2)
264 #define PLLP_OUT2_OVR		(1 << 18)
265 #define PLLP_OUT3_OVR		(1 << 2)
266 #define PLLP_OUT4_OVR		(1 << 18)
267 #define PLLP_OUT1_RATIO		8
268 #define PLLP_OUT2_RATIO		24
269 #define PLLP_OUT3_RATIO		8
270 #define PLLP_OUT4_RATIO		24
271 
272 enum {
273 	IN_408_OUT_204_DIVISOR = 2,
274 	IN_408_OUT_102_DIVISOR = 6,
275 	IN_408_OUT_48_DIVISOR = 15,
276 	IN_408_OUT_9_6_DIVISOR = 83,
277 };
278 
279 #define PLLP_OUT1_RSTN_DIS	(1 << 0)
280 #define PLLP_OUT1_RSTN_EN	(0 << 0)
281 #define PLLP_OUT1_CLKEN		(1 << 1)
282 #define PLLP_OUT2_RSTN_DIS	(1 << 16)
283 #define PLLP_OUT2_RSTN_EN	(0 << 16)
284 #define PLLP_OUT2_CLKEN		(1 << 17)
285 
286 #define PLLP_OUT3_RSTN_DIS	(1 << 0)
287 #define PLLP_OUT3_RSTN_EN	(0 << 0)
288 #define PLLP_OUT3_CLKEN		(1 << 1)
289 #define PLLP_OUT4_RSTN_DIS	(1 << 16)
290 #define PLLP_OUT4_RSTN_EN	(0 << 16)
291 #define PLLP_OUT4_CLKEN		(1 << 17)
292 
293 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
294 #define PLLU_POWERDOWN		(1 << 16)
295 #define PLL_ENABLE_POWERDOWN	(1 << 14)
296 #define PLL_ACTIVE_POWERDOWN	(1 << 12)
297 
298 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
299 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN		(1 << 4)
300 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
301 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
302 
303 /* CLK_RST_CONTROLLER_OSC_CTRL_0 0x50 */
304 #define OSC_XOE_SHIFT			0
305 #define OSC_XOE_MASK			(1 << OSC_XOE_SHIFT)
306 #define OSC_XOE_ENABLE			(1 << OSC_XOE_SHIFT)
307 #define OSC_XOBP_SHIFT			1
308 #define OSC_XOBP_MASK			(1U << OSC_XOBP_SHIFT)
309 #define OSC_XOFS_SHIFT			4
310 #define OSC_XOFS_MASK			(0x3F << OSC_XOFS_SHIFT)
311 #define OSC_DRIVE_STRENGTH		7
312 
313 /*
314  * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
315  * but can be 16. We could use knowledge we have to restrict the mask in
316  * the 8-bit cases (the divider_bits value returned by
317  * get_periph_clock_source()) but it does not seem worth it since the code
318  * already checks the ranges of values it is writing, in clk_get_divider().
319  */
320 #define OUT_CLK_DIVISOR_SHIFT	0
321 #define OUT_CLK_DIVISOR_MASK	(0xffff << OUT_CLK_DIVISOR_SHIFT)
322 
323 #define OUT_CLK_SOURCE_31_30_SHIFT	30
324 #define OUT_CLK_SOURCE_31_30_MASK	(3U << OUT_CLK_SOURCE_31_30_SHIFT)
325 
326 #define OUT_CLK_SOURCE_31_29_SHIFT	29
327 #define OUT_CLK_SOURCE_31_29_MASK	(7U << OUT_CLK_SOURCE_31_29_SHIFT)
328 
329 /* Note: See comment for MASK_BITS_31_28 in arch-tegra/clock.h */
330 #define OUT_CLK_SOURCE_31_28_SHIFT	28
331 #define OUT_CLK_SOURCE_31_28_MASK	(15U << OUT_CLK_SOURCE_31_28_SHIFT)
332 
333 /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */
334 #define SCLK_SYS_STATE_SHIFT    28U
335 #define SCLK_SYS_STATE_MASK     (15U << SCLK_SYS_STATE_SHIFT)
336 enum {
337 	SCLK_SYS_STATE_STDBY,
338 	SCLK_SYS_STATE_IDLE,
339 	SCLK_SYS_STATE_RUN,
340 	SCLK_SYS_STATE_IRQ = 4U,
341 	SCLK_SYS_STATE_FIQ = 8U,
342 };
343 #define SCLK_COP_FIQ_MASK       (1 << 27)
344 #define SCLK_CPU_FIQ_MASK       (1 << 26)
345 #define SCLK_COP_IRQ_MASK       (1 << 25)
346 #define SCLK_CPU_IRQ_MASK       (1 << 24)
347 
348 #define SCLK_SWAKEUP_FIQ_SOURCE_SHIFT		12
349 #define SCLK_SWAKEUP_FIQ_SOURCE_MASK		\
350 		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
351 #define SCLK_SWAKEUP_IRQ_SOURCE_SHIFT		8
352 #define SCLK_SWAKEUP_IRQ_SOURCE_MASK		\
353 		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
354 #define SCLK_SWAKEUP_RUN_SOURCE_SHIFT		4
355 #define SCLK_SWAKEUP_RUN_SOURCE_MASK		\
356 		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
357 #define SCLK_SWAKEUP_IDLE_SOURCE_SHIFT		0
358 
359 #define SCLK_SWAKEUP_IDLE_SOURCE_MASK		\
360 		(7 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT)
361 enum {
362 	SCLK_SOURCE_CLKM,
363 	SCLK_SOURCE_PLLC_OUT1,
364 	SCLK_SOURCE_PLLP_OUT4,
365 	SCLK_SOURCE_PLLP_OUT3,
366 	SCLK_SOURCE_PLLP_OUT2,
367 	SCLK_SOURCE_CLKD,
368 	SCLK_SOURCE_CLKS,
369 	SCLK_SOURCE_PLLM_OUT1,
370 };
371 #define SCLK_SWAKE_FIQ_SRC_PLLM_OUT1    (7 << 12)
372 #define SCLK_SWAKE_IRQ_SRC_PLLM_OUT1    (7 << 8)
373 #define SCLK_SWAKE_RUN_SRC_PLLM_OUT1    (7 << 4)
374 #define SCLK_SWAKE_IDLE_SRC_PLLM_OUT1   (7 << 0)
375 
376 /* CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER */
377 #define SUPER_SCLK_ENB_SHIFT		31U
378 #define SUPER_SCLK_ENB_MASK		(1U << 31)
379 #define SUPER_SCLK_DIVIDEND_SHIFT	8
380 #define SUPER_SCLK_DIVIDEND_MASK	(0xff << SUPER_SCLK_DIVIDEND_SHIFT)
381 #define SUPER_SCLK_DIVISOR_SHIFT	0
382 #define SUPER_SCLK_DIVISOR_MASK		(0xff << SUPER_SCLK_DIVISOR_SHIFT)
383 
384 /* CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30 */
385 #define CLK_SYS_RATE_HCLK_DISABLE_SHIFT 7
386 #define CLK_SYS_RATE_HCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT)
387 #define CLK_SYS_RATE_AHB_RATE_SHIFT     4
388 #define CLK_SYS_RATE_AHB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
389 #define CLK_SYS_RATE_PCLK_DISABLE_SHIFT 3
390 #define CLK_SYS_RATE_PCLK_DISABLE_MASK  (1 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT)
391 #define CLK_SYS_RATE_APB_RATE_SHIFT     0
392 #define CLK_SYS_RATE_APB_RATE_MASK      (3 << CLK_SYS_RATE_AHB_RATE_SHIFT)
393 
394 /* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */
395 #define CLR_CPURESET0			(1 << 0)
396 #define CLR_CPURESET1			(1 << 1)
397 #define CLR_CPURESET2			(1 << 2)
398 #define CLR_CPURESET3			(1 << 3)
399 #define CLR_DBGRESET0			(1 << 12)
400 #define CLR_DBGRESET1			(1 << 13)
401 #define CLR_DBGRESET2			(1 << 14)
402 #define CLR_DBGRESET3			(1 << 15)
403 #define CLR_CORERESET0			(1 << 16)
404 #define CLR_CORERESET1			(1 << 17)
405 #define CLR_CORERESET2			(1 << 18)
406 #define CLR_CORERESET3			(1 << 19)
407 #define CLR_CXRESET0			(1 << 20)
408 #define CLR_CXRESET1			(1 << 21)
409 #define CLR_CXRESET2			(1 << 22)
410 #define CLR_CXRESET3			(1 << 23)
411 #define CLR_L2RESET			(1 << 24)
412 #define CLR_NONCPURESET			(1 << 29)
413 #define CLR_PRESETDBG			(1 << 30)
414 
415 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */
416 #define CLR_CPU0_CLK_STP		(1 << 8)
417 #define CLR_CPU1_CLK_STP		(1 << 9)
418 #define CLR_CPU2_CLK_STP		(1 << 10)
419 #define CLR_CPU3_CLK_STP		(1 << 11)
420 
421 /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */
422 #define MSELECT_CLK_SRC_PLLP_OUT0	(0 << 29)
423 
424 /* CRC_CLK_ENB_V_SET_0 0x440 */
425 #define SET_CLK_ENB_CPUG_ENABLE		(1 << 0)
426 #define SET_CLK_ENB_CPULP_ENABLE	(1 << 1)
427 #define SET_CLK_ENB_MSELECT_ENABLE	(1 << 3)
428 
429 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 0x484 */
430 #define PLL_ACTIVE_POWERDOWN		(1 << 12)
431 #define PLL_ENABLE_POWERDOWN		(1 << 14)
432 #define PLLU_POWERDOWN			(1 << 16)
433 
434 /* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 0x488 */
435 #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN	(1 << 0)
436 #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN	(1 << 2)
437 #define UTMIP_FORCE_PD_SAMP_C_POWERDOWN	(1 << 4)
438 
439 /* CLK_RST_CONTROLLER_PLLX_MISC_3 */
440 #define PLLX_IDDQ_SHIFT			3
441 #define PLLX_IDDQ_MASK			(1U << PLLX_IDDQ_SHIFT)
442 
443 #endif	/* _TEGRA_CLK_RST_H_ */
444